Part of the Consumer Audio Solutions group, responsible for definition of next generation hearable Audio SoCs. Focused on earbud, headset, and AR/VR applications. Involved in understanding the audio application space, defining the SoC architecture, triaging the compute IP eco-system, and collaborating with customers and partners to develop powerful embedded audio SoCs with exceptional power efficiency for hearable products. Collaborating on the definition of next generation architectures, IP and SoC, focused on recursive NN audio processing and low latency audio processing. Driving the full signal chain from physical phenomena sampling, through SoC architecture, to embedded SW development work flow and tool chain. Solving challenges and delivering thought-leadership in ML NR, spatialization, ANC, hearing transparency/augmentation, along with a rich set of traditional features. Balancing power, performance, and cost for an ever increasing number of customer usecases in the hearable application space.

Responsible for defining and driving DSP Concepts' hearable and wearable product offerings. Reporting to the CTO & Founder, collaborating with external partners and internal disciplines to enable OEMs to deliver innovative audio features to the market FAST. Focused on developing a TWS reference design, with a rich 3rd party eco-system, in Audio Weaver to exceed the complex requirements of next gen products.

Briefly lead the SoC power architecture team for Client products. Audited existing power estimation and SoC power modeling process & methodologies. Developed comprehensive training for power architects and team, redefining roles/responsibilities/dynamics with various cross-functional teams. Identified opportunities for improvement, modernization, and greater efficiency. Established requirements/expectations for greater Quality of Results (QoR) and crafted the plan to achieve it. Developed extensive collateral and conducted training to the Client SoC power architecture, power execution, and cross-functional teams. Mentored team to develop best-in-class low power products in a highly competitive product space.

Responsible for investigating new technology (SW and HW) and enabling new applications on Ambiq's industry leading low power SoCs. Led R&D activities in the CTO's office enabling a variety of wearable and hearable features such as embedded Voice User Interfaces (VUI) w/ sound enhancement, Active Noise Cancellation (ANC), embedded ML inference, Pedestrian Dead Rekoning (PDR) w/ GPS fusion, biometric authentication, and sensor fusion. Focused on developing partner relationships to create innovative solutions for both current and future products. Leveraging Ambiq's partner network to enable customer products to achieve longer battery life and bringing always-on processing to the edge (wearable, hearable, and IoT devices). Performed technical due diligence for embedded core, algorithm, and SW IP selection. Austin TinyML Meetup co-corrdinator.

Involved in the development of the world’s lowest power MCU for Wearable & IoT applications as a power architect reporting to the CTO & Founder.Responsible for reducing energy consumption while doing useful things in our products.Responsible for enabling new functions with our products that were previously prohibited due to battery life constraints.Exploring feature and energy innovations in Si, Software, and Systems.Part of the Advanced Development Team focused on next generation product definition, new technology adoption, and market specific optimizations.

Developing SoCs for multiple generations of high-end smartphone and wearable products.Responsible for modeling and estimating power for the SoC in a variety of applications. Performing component centric to full chip architectural analysis in order to balance power and performance. Defining power delivery specifications. Participant in external IP SoW authoring.Contributor in a large team estimating platform level power/performance/thermals and performing tradeoff analysis involving low-level HW to application level SFW. Participant in RFI/RFQ authoring.SoC power lead responsible for the operational and technical management of the pre-silicon power team. Coordinating multiple disciplines to both provide deliverables to estimate power and drive convergence to power targets. Driving pre- and post-silicon power correlation and optimizations to meet targets. Triaging critical issues late in program to determine optimal tradeoff.

Involved in the development of WiMedia Ultrawideband wireless chipsets. Chipsets are integrated RF and digital SoCs as well as smart-partitioned digital SoCs with converters.Responsible for the re-architecture of the previous MAC for performance and area. Architecting the next generation MAC for enhanced throughput and additional features. Familiar with the WiMedia and the Wireless USB specifications. Working closely with the software team to partition the application between hardware and firmware.

Co-founded a startup focused on the development of wireless video distribution solutions.Collaborated in planning the development strategy, cost, and organization of the venture.

Led the development of 2 generations of JPEG 2000 image codec SoCs. Involved from product definition to cost reduction after release. Owned balancing product features, FFC, schedule, and development cost.Responsible for coordinating activities of all the disciplines (marketing, software, PE, etc.) involved in a SoC development to plan, gain approval/funding, and execute on development. Managed schedule and requirement changes.Drove the adoption of design services for chip implementation. Negotiated the terms of the engagement, managed IP transfer, and managed the relationship. Led the ADI implementation effort to achieve timing closure. Collaborated with packaging team to develop BGA and SiP packages.Owned ARM7 and ARM9 based CPU sub-system definition, design, and integration.Involved in market and standards development through active participation in CEA, HANA, and 1394TA.

Led the digital design effort of a mixed-signal SoC. The product was an integrated CMOS AFE/TG and ISP SoC. Part of an international, multi-corporation development team. Involved from product definition to customer evaluation.Collaborated in defining product development strategy. Development involved FPGA prototype followed by IC development. Actively involved in FPGA logic development and debug in hardware. Led silicon bring-up effort.Managed definition and logistics of SoC deliverables to/from sites and external partner. Defined and documented digital design, verification, and implementation work flows. Implemented project simulation development environment at each site. Trained and mentored on-site and remotely. Owned ARM7 based CPU sub-system defintion, design, and integration.Continued responsibility for chip integration and golden model management. Developed initial top-level testbench and full-chip level tests.

Involved in the development of a JPEG2000 image codec SoC from product definition to post release cost reduction. Re-architected the wavelet transform block for increased performance and resolution. Owned ARM7 based CPU sub-system design and integration. Principle design team interface to software for boot, production, and verification environment firmware. Responsible for chip integration. Responsible for golden model build and promotion. Developed initial top-level testbench and tests. Enhanced simulation development environment. Developed and debugged full-chip level tests. Responsible for mentoring team in new verification strategy centered on a CPU sub-system.Led implementation effort. Specifically responsible for synthesis, scan insertion, ATPG, coverage, CTS, equivalence, and gate simulation. Collaborated with packaging team to develop two BGA packages.Led Silicon Bring-up effort. Worked with test engineer to evaluate 1st silicon on test floor.

Involved in the development of a mixed-signal SoC. Part of an international development team. Gained significant experience and insight in multi-site, international product development.Developed components of I/O sub-sytem: I2C, GPIO, data managment units. Developed complete synthesis environment for the CPU sub-system for IP hand-off.

Led the implementation effort of the 1st JPEG2000 Image Codec. Involved from product definition to release.Responsible for glue-logic design and chip integration. Developed initial top-level testbench and tests. Coordinated the efforts of the implementation team and managed schedule. Specifically responsible for RTL to gate synthesis, gate optimization, CTS, RTL to gate equivalence, and gate simulation in the implementation effort.

Involved in the development of a 2nd generation Floating-Point DSP, Graphics Accelerator SoC, and Wavelet Video Codec.Developed MMU blocks and components of a I/O sub-sytem: SPI, data managment units. Designed and implemented multiple metal-only ECOs. Implemented and operated automated test environment generating random test stimulus with self-checking support.