Arpit Shah Email & Phone Number

Cambridge, Cambs, GB

Wilmington, MA, US

Part of the Consumer Audio Solutions group, responsible for definition of next generation hearable Audio SoCs. Focused on earbud, headset, and AR/VR applications. Involved in understanding the audio application space, defining the SoC architecture, triaging the compute IP eco-system, and collaborating with customers and partners to develop powerful.

Santa Clara, California, US

Responsible for defining and driving DSP Concepts' hearable and wearable product offerings. Reporting to the CTO & Founder, collaborating with external partners and internal disciplines to enable OEMs to deliver innovative audio features to the market FAST. Focused on developing a TWS reference design, with a rich 3rd party eco-system, in Audio Weaver to.

Santa Clara, California, US

Briefly lead the SoC power architecture team for Client products. Audited existing power estimation and SoC power modeling process & methodologies. Developed comprehensive training for power architects and team, redefining roles/responsibilities/dynamics with various cross-functional teams. Identified opportunities for improvement, modernization, and.

Austin, Texas, US

Responsible for investigating new technology (SW and HW) and enabling new applications on Ambiq's industry leading low power SoCs. Led R&D activities in the CTO's office enabling a variety of wearable and hearable features such as embedded Voice User Interfaces (VUI) w/ sound enhancement, Active Noise Cancellation (ANC), embedded ML inference, Pedestrian.

Austin, Texas, US

Involved in the development of the world’s lowest power MCU for Wearable & IoT applications as a power architect reporting to the CTO & Founder.Responsible for reducing energy consumption while doing useful things in our products.Responsible for enabling new functions with our products that were previously prohibited due to battery life.

Santa Clara, California, US

Developing SoCs for multiple generations of high-end smartphone and wearable products.Responsible for modeling and estimating power for the SoC in a variety of applications. Performing component centric to full chip architectural analysis in order to balance power and performance. Defining power delivery specifications. Participant in external IP SoW.

Austin, TX, US

Involved in the development of WiMedia Ultrawideband wireless chipsets. Chipsets are integrated RF and digital SoCs as well as smart-partitioned digital SoCs with converters.Responsible for the re-architecture of the previous MAC for performance and area. Architecting the next generation MAC for enhanced throughput and additional features. Familiar with.

Co-founded a startup focused on the development of wireless video distribution solutions.Collaborated in planning the development strategy, cost, and organization of the venture.

Wilmington, MA, US

Led the development of 2 generations of JPEG 2000 image codec SoCs. Involved from product definition to cost reduction after release. Owned balancing product features, FFC, schedule, and development cost.Responsible for coordinating activities of all the disciplines (marketing, software, PE, etc.) involved in a SoC development to plan, gain.

Wilmington, MA, US

Led the digital design effort of a mixed-signal SoC. The product was an integrated CMOS AFE/TG and ISP SoC. Part of an international, multi-corporation development team. Involved from product definition to customer evaluation.Collaborated in defining product development strategy. Development involved FPGA prototype followed by IC development. Actively.

Wilmington, MA, US

Involved in the development of a JPEG2000 image codec SoC from product definition to post release cost reduction. Re-architected the wavelet transform block for increased performance and resolution. Owned ARM7 based CPU sub-system design and integration. Principle design team interface to software for boot, production, and verification environment.

Wilmington, MA, US

Involved in the development of a mixed-signal SoC. Part of an international development team. Gained significant experience and insight in multi-site, international product development.Developed components of I/O sub-sytem: I2C, GPIO, data managment units. Developed complete synthesis environment for the CPU sub-system for IP hand-off.

Wilmington, MA, US

Led the implementation effort of the 1st JPEG2000 Image Codec. Involved from product definition to release.Responsible for glue-logic design and chip integration. Developed initial top-level testbench and tests. Coordinated the efforts of the implementation team and managed schedule. Specifically responsible for RTL to gate synthesis, gate optimization.

Wilmington, MA, US

Involved in the development of a 2nd generation Floating-Point DSP, Graphics Accelerator SoC, and Wavelet Video Codec.Developed MMU blocks and components of a I/O sub-sytem: SPI, data managment units. Designed and implemented multiple metal-only ECOs. Implemented and operated automated test environment generating random test stimulus with self-checking.

Bsee, Electrical Engineering

Electrical Engineering