CAD/PDK Engineering Manager and Senior Technical Lead Engineer working in Intel Foundry currently driving multiple technical contributors to a common department goals and integrated accomplishments. Own complete EM/IR tool PDK platform enablement for Intel internal & Intel External Foundry customers. Having hands on experience in front end circuit verification domains such as analog/digital characterization tools and flows, RC parasitic extraction tools and flow support - deep dive debug and route causing, Custom RV (EM/IR) tool/flow support, ASIC/Digital RV (EM/IR) in depth tool enablement in new process nodes, Spice golden reference for ASIC/Digital EM/IR tools, version to version tool/CAD qualification, Top EDA vendor platform in ASIC RV - Ansys Redhawk-SC & Cadence Voltus, PERC rule deck validation platform in parallel three top EDA vendors - new enablement, extensive experience in CAD tools qualifications and driving strategic initiatives in team.Currently expanding into multi die 3DIC Reliability Validation (EM/IR), simultaneous multi die analysis in RV analysis at leading edge technology.Working on Intel Foundry Industry standardization of High Voltage Electrical Overstress checks for both Synopsys and Cadence platform offering - Moving from conventional PERC based topological voltage propagation to Industry standard tools like Synopsys CCK & cadence spectre High voltage checks.