> Trained in physical design at Sumedha IT> Experience with process nodes such as 28nm> Good knowledge in Synthesis,STA,PnR> Analysed the Timing reports and reported the cause of error for the timing violations.> Understanding the design specifications and designing of Floorplan accordingly such that to have a contagious core area for standard cell placement.> Placement and Optimization of tap cells, boundary cells and standard cells to meet the DRC violations and Congestion check.