• Pre-silicon driver development and integration for I2C, UART, DIO, System control, and PDM• Wrote automation test package for Pulsar (logic analyzer) and integrated into board bring-up• Achieved 100% code coverage with unit tests and wrote Misra-C-compliant code using static analysis

• Leading firmware design for 5-node distributed system managing BMS, power-distribution, and telemetry systemsSTM32L4 Cortex-M4 Board Bring-up• Created thread-safe protocol APIs, linker scripts, hard-fault register dump, and compiler flags to reduce code size 8%FreeRTOS Implementation• Implemented FreeRTOS wrappers for task declarations, semaphores, queues, and event-driven timer management• Architected 1kHz, 100Hz, and 10Hz RTOS architecture, ensuring deterministic task scheduling and interrupt handlingBattery Management System• Developed LTC6811-based BMS firmware managing 288 cells (8P36S), 150V and 52A system, with passive balancing, multi-thermistor monitoring and over-charge protection• Implemented SOC estimation using discrete-time coulomb counting and voltage maps through automated HV testingPower Distribution• Designed power-distribution firmware with multiplexed low-voltage rails and overcurrent protection for 20 channels• Engineered power sequencing state machine with pre-charge management for 150V motor system and solar arrayCAN Autogen and Infrastructure• Automated CAN infrastructure with Python-based DBC generation and runtime analysis tools for multi-MCU network• Implemented priority-handling, message filtering, and configurable rate of transmissions using Jinja and YAML files System Integration/Design• Reduced CPU consumption through optimized interrupt-driven architectures • Engineered vehicle firmware mock-up, reducing board validation time by 40%

• Engineered BMS firmware managing 288 cells with passive balancing and multi-sensor protection systems• Developed power sequencing FSM with pre-charge interlocks for 150V motor system, reducing complexity by 60%• Implemented one-pedal drive with dynamic regenerative braking, extending race duration by 13% in drive tests• Validated I2C, SPI, and CAN transactions with register-level debugging using GDB, logic analyzers, and oscilloscopes