Arash Shakeri Email & Phone Number

Cupertino, California, Us

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Ridgefield Park, Nj, Us

• Manage all the HW, product, and mechanical development activities for the digital health group under regulatory considerations and FDA process (60601-x-x)• Select, negotiate with, and manage sub-contractors and contract manufacturers involved in development and manufacturing of the products, reference platforms, and modules• Provide technical review and oversight on the development of all sensor sub-systems including custom build sensors for the product• Provide technical direction to engineering teams working on development and validation of various biometric sensors including PPG arrays, ECG, BioZ, and GSR• Interface with and coordinate all the vendors (components, manufacturing, tooling, design services, environmental testing, and certification) to ensure on time delivery of solutions and products• Manage and coordinate all the NPI activities including contracts with overseas manufacturing, budgeting, forecasting, and logistics• Recruit, develop, and maintain talent in hardware, mechanical, and validation engineering roles

Santa Clara, Ca, Us

• Led the design team providing technical oversight on all the engineering efforts for Nvidia's first major consumer product Nvidia Shield (http://shield.nvidia.com/store/portable) with specific focus on all the user facing sub systems• Authored several RFQs including custom LCD and custom Touch Panel and camera module. Negotiated with all the major LCD, Touch panel, and camera module manufacturers to select the right solution• Participated in definition, architecture, and execution of Project Shield • Provided top level summaries to management while influencing product level decisions • Interfaced with internal teams: platform, mechanical, software, and Tegra SOC as well as external vendors such as LCD and touch manufacturers driving resolutions to challenges and issues • Audited the cost and performance of sub designs to ensure they remained in alignment with the competitive niche they were intended to occupy

Santa Clara, California, Us

• Designed and implemented power aware circuits for the IO blocks to ensure glitch free operation regardless of power up sequencing (TSMC28nm)• Designed AMD’s next generation GPIO receiver blocks with innovative high voltage tolerances (GF28nm)• Redesigned the power sniffer blocks increasing detection threshold with minimal area and power penalty

Santa Clara, California, Us

• Provided technical leadership and oversight and was responsible to deliver several concurrent projects from enthusiast (high margin) to mainstream (high volume) products• Recipient of AMD’s Spirit of Success Award (the highest award given to an individual contributor) for delivering Eyefinity technology to market• Architected and delivered a cross functional project ( GPU Star Dust) which enabled GPU platforms to use a CPU purposed tool speeding up power delivery path characterization• Represented Platform team in cross functional meetings where high level decisions were made• Supervised and mentored team members ensuring consistency and quality across projects• Led GPU platform in tool alignment and consolidation with CPU team. This resulted in adoption of cost estimation techniques by the CPU team, as well as GPU teams’ adoption of CPU schematics design tools and processes

Santa Clara, Ca, Us

• Actively participated in the entire NPI cycle from creating specifications, architecture and design of the board, BOM creation, and bring up. Also supervised board qualification and production release.• Served as Lead Design Engineer for multiple graphics boards, ranging from value segment 4 layer boards to high end enthusiast 12 layer designs• Designed and qualified cost effective SMPS and LDO power supplies for various platforms• Recognized as one of the most cost conscious designers leading many projects to completion under budget and ahead of schedule contributing to better than forecasted gross margins

San Jose, Ca, Us

• Designed test boards, developed and synthesized Verilog code on Xilinx FPGA (Virtex II), and developed Perl scripts and Verilog code as test and functional models for two ASICs in development• Designed and implemented a Multicast test system incorporating IP/TV technology.• Completed training in: Deep Knowledge in Verilog Synthesis, Specman Elite, TCP/IP technologies, Fiber Optics, IXIA, and SMATBITS packet generation training

New York, New York, Us

•• Deployed and maintained the bank’sLAN/WAN systems, multi-protocol routers, repeaters, hubs, and encryption devices.• Designed and implemented a virtual Token Ring network to provide redundant mainframe connectivity• Attended training in: Cisco VPN, EcoScope network monitoring utilities, MS Access, and Microsoft SMS