Ashish Ghai Email & Phone Number

Singapore

Boise, Idaho, Us

San Jose, Ca, Us

 Led Product Engineering global team of 30+ engineers with 5 managers supporting the Enterprise SSD Product Line, with a focus on Memory/System Test Leadership in Innovation, Quality, Cost, Cycle-Time and Delivery Product Line Core Team Lead representing Product & Test Engineering Activities which include Drive Test, Memory Test, Manufacturing Firmware, and Failure Analysis global teams. Bridged Development and Operation teams for NPI and Product Life Cycle Management to ensure new product realization and time to market. Defined test strategy and test development framework for high volume Enterprise SSD Manufacturing with effective cost scaling. Achieved target KPIs (DPPM, Yield, Cycle Time) for the complete production flow. Defined Systematic Product and Test Framework for Shift Left Strategies, in areas of HW Test Coverage improvement via DFT/DFM, Quality Improvement, Drive Test and MFG FW QA and regression environments, NAND and Drive-System Optimized Test Flows, Silicon Instrumentation for blind build issue prevention and pre-FW availability testing, Lost Cost Testing Interface Exploration. Orchestrated incremental and disruptive innovations towards the paradigm of Test vs Bit Scaling with low cost Self Test Solutions for 3D NAND Memory and Enterprise SSD Drives, along with N Bit Scaling Strategies by incorporating Machine Learnings and predictions methodologies. Created the Technology Staging Initiative focused towards technology Enablement, HW Component Characterization and Futuristic Projects and built a Scaled Agile Framework (SAFE) around each of these initiatives. Initiatives include Edge Die Wafer Recovery for Retail and OEM Product Lines, NAND Die and System Component characterization. Machine Learning/Deep Learning for Failure Analysis, Yield Improvement and Test Time Reduction and NAND Die Life Prediction.

Milpitas, Ca, Us

 Provided technical and strategic guidance, business analysis and project management capabilities to fuel the success of the advanced R&D Team within the Product and Test Engineering Department. Launched and effectively lead a team of 6 onsite and 3 offsite individuals in driving the development . of 3D NAND 3-bit per cell NAND FLASH Technology geared towards reducing the Defective Part Per . Million (DPPM) along with improving the Endurance and Data Retention specifications, by tailoring to the needs to various customers such as Component Customers (Apple, Huawei, LG), Customer SSD (CSS), Enterprise (SSD), and Retail (uSD, USB, SD)  Spearheaded the R&D of a new Firmware based Wafer Platform by forming a cross functional hardware, software and firmware team focused in creating new System Algorithms focused towards NAND defect management and prediction. The new testing platform decreased the R&D Development and Production time by 35%. Established a highly productive Wafer Level Reliability Automated infrastructure process and provided technical and project management guidance to a team of individuals in automating the characterization of the DPPM and hence improving the process efficiency by 30% Worked collaboratively with operations and technology teams and provided technical and strategic solutions to bridge the gap between RnD and Manufacturing and provide high yielding and reliable world leading (15nm, 3D) NAND Products. Led the initiative of improving Data Analytics/Data sharing by becoming a key contributor to the Big Data initiative at SanDisk and hence devised new methodologies targeted towards using Hadoop/SPARK based distributed programming paired with Machine Learning to help solve various use cases

Milpitas, Ca, Us

 Worked in the development of SLC, 3-bit, 4-bit MLC NAND Flash Products from 56nm to 15nm process nodes and assisted different teams, from Design to Qualification. Responsible for the first silicon debug and characterization to validate Design/Device/Process specification. Designed Memory Test Production Flow encompassing Stress/Screens pertaining to Memory Reliability. Performed Electrical Failure Analysis (EFA) and worked with Physical Failure Analysis team to understand root cause and enhance countermeasures. Performed trim optimization to improve the key NAND Reliability metrics such as endurance and data retention without compromising the part performance. Validated, alongside with the FAB Product Engineering/Process Integration/QA Teams, the release of FAB Process/Design/Device Changes pertaining to cell reliability, endurance, data retention characteristics, physical defects or cost reductions. Worked with Design/Device/Process Integration/FAB Teams and fed back the various memory issues in order to improve the process and thereby improve manufacturing yields. Created the Wafer Level Reliability Automation infrastructures by developing Software for in house Wafer Level Memory Testing in order to quantify the health of memory by automatically characterizing the DPPM for different Array and Periphery failure modes. Facilitated the Fail Mode Classification by designing an automated EFA Software Engine. Resolved customer related issues alongside RMA Engineers and carried out any special data requests. Setup offshore PE Teams and trained them in the concepts of NAND Flash and PE roles and responsibility. Designed the Firmware Memory Diagnostic Layer and code for Memory Testing in a System Infrastructure. Developed System Test code for Sony Memory Stick and SD product line to do performance testing. Performed Analysis on System Qualification Failures and developed firmware based solutions.

Santa Clara, California, Us

 Designed local and system level test-benches using a combination of perl, verilog and C PLI, Assert Based Verification techniques (PSL), code coverage and waveform viewers. Formulated C/C++ based models for the system level blocks for emulation. Documented the implementation and usage guidelines of the test-benches within user manuals. Conducted meetings with hardware designers to provide updates on tasks and get new design verification related tasks. Coordinated Design Verification information sessions for the new hires and provided one-on-one training. Utilized a system-on-chip builder tool for creating systems based on processors, peripherals & memories. Designed the makefile infrastructure flow used for compiling, assembling and linking the C/C++ code for the microprocessor. Composed C/C++ code for the microprocessor to test the data and instruction buses. Created system prototypes and provided them to the hardware and software teams for testing purposes

Master Of Science - Ms, Engineering Management And Leadership

Basc, Electrical Engineering