R&D RTL Design Engineer – Beamforming IP Development for 8T8R Macro RU1) Led RTL design for Beamformer State Machine, Counter Logic, and key sub-blocks using Verilog HDL. 2) Integrated Oran-fronthaul IP with Low-phy, ECPRI, and other modules. 3) Managed multiple clock domains and high-speed clocks up to 491.52 MHz, ensuring timing compliance through static timing analysis. 4) Resolved clock domain crossing (CDC) issues to achieve timing closure. 5) Achieved FPGA timing closure at 491.52 MHz, improving WNS from -2.158ns to 0.005ns. 6) Collaborated effectively to drive problem-solving and meet milestones. 7) Hands-on experience with AMBA protocols, including AXI and SPI.

1) Leveraged industry-standard front-end tools for RTL coding, synthesis, implementation, and bitstream generation, while also performing board debugging using Integrated Logic Analyzer (ILA) and sending packets via VIO, ensuring an optimized FPGA design flow.2) Gained hands-on experience with AMBA protocols, including AXI and SPI.3) Contributed to the development of the USER INTERLEAVER and played a key role in unifying its functionality within the Xilinx UltraScale+ RFSoC FPGA, utilizing various Xilinx IPs like BRAM, FIFOs, and URAM.

Analog Systems and Lab (Jan 2022-may 2023)

RTL Design