Sound knowledge of Functional Verification principles and Digital System Design.-- Knowledge in writing fully Automated and Reusable Testbench. -- Knowledge in writing Monitor, Driver, Checker, Test controllers, Functional Coverage collector.-- Experience with full chip verification environment dealing right from Implementation of verification environment-- Supporting Creation of test plan, test pattern generations.-- Creating assertion plan and writing system Verilog assertions checkers.-- Verified the design at the module level and full chip level.-- Experience in verification for NAND 3D flash memory using System Verilog Assertions-- Experience in developing the appropriate test cases using UVM for full chip environment and interrupt cases -- Experience in Developing the Coverage models