Frank Bruno Email & Phone Number

Confidential

World, Free, OO

Traveling. Ask me about China, Switzerland and Iceland

Chicago, IL, US

Developing FPGAs for trading infrastructure.

San Francisco, California, US

Helping to make self driving vehicles a reality!Zynq MPSOC development - cameras, ECC & batting cleanup. Timing closure and master of SPAM.Learning Linux kernel drivers on the job.

Developed FPGA exchange parsersDeveloped FPGA based orderbooks, both level and order basedMicrowave link interface designs to maximize utilization and first to transmitTiming closure for multi-SLR designs running at > 350Mhz

Hawthorne, California, US

Did my part to help make humanity an interplanetary species."SpaceX is like Special Forces… we do the missions that others think are impossible. We have goals that are absurdly ambitious by any reasonable standard, but we’re going to make them happen. We have the potential here at SpaceX to have an incredible effect on the future of humanity and life.

Franklin, Massachusetts, US

FPGA Design and Architecture for multipart 10G/100G ethernet packet inspection.Developed high speed packet parser to strip MPLS and VLAN tags.Developed 100G IDLE packet generator for LR4 & SR10.http://accoladetechnology.com

Delivered 4 channel Zynq SOC FPGA based SDR in a little over a year. The SDR utilized an ADI 9361 and custom RF.Drove the architecture and implementation by leading a team of 4 design and verification engineers.Experience with AXI interconnect and architecture.Implemented overlap and save based correlation for FFT based preamble detect based on Zadoff-Chu.

Incorporated company to sell FPGA based graphics accelerator cores based upon Number Nine IP licensed from holding company. Redesigned IP to be a fully synchronous and safe design. Experience with floating point math including multiply, divide and addition. Drove sales by attending tradeshows and conferences to demonstrate IP in operation.Experienced with.

Christchurch, Dorset, GB

Formerly MA/COMLead FPGA Engineer for Cobham SR&DArchitected, designed, verified FPGA switch fabric for Next generation software defined radio system.Team lead for 6 FPGA design/ DV engineers.

Wilmington, MA, US

Improved the design flow for low power metering ASIC by converting hand instantiated logic into synthesizable Verilog and implementing a fully automated P&R flow. Introduced low power methodologies such as clock gating and scan across power/ clock domains. UPF flow from RTL to tapeout.

Sunnyvale, California, US

Drove SystemVerilog usage amongst Synopsys customers in the Northeast by demonstrating Synopsys’ lead in embracing the language. Improved customer utilization of Synopsys tools increasing sales. Supported customer tapeouts for 65nm designs by demonstrating tool capabilities in low power design and Primetime multi corner analysis.

Santa Clara, CA, US

Architected GFP Framer/ DeFramer chipset and stand-alone device. 400Mhz framing operation and 311Mhz Deframing. Designed efficient re-usable store and forward FIFOs. Ported OC12 ATM to OC48 opertion.

US

Architected and led design of three router expansion ASICs. Led FPGA Design effort for new router design. Gate level debug of vendor high speed PLL lock detect circuit.

Architected and designed major portions of High Speed, High Gate count Graphics Processors including pixel and texture caches, IEEE floating point units (Add, Multiply and Reciprocal) and 3D operations. Responsible for Synthesis, floor planning and Static Timing Analysis.

London, GB

ASIC/ VHDL go-to guy.Designed 60K gate ASIC for F22 EW program.System simulations, synthesis, debug.

Msee, Electrical Engineering

Ai For Trading Nanodegree, Computer Engineering

Bachelor'S Degree, Electrical Engineering

Further Course Work, Computer Engineering

Mba, Marketing, Business Administration