Memory and IO Subsystem

Memory Subsystem

Memory Subsystem

Research and Architecture for the next generation AI accelerator to support use cases in 5G, networks, switches, automobiles etc. Micro-architecture specification for the previous generation core compute cluster ASIC, designed to accelerate machine learning inference. RTL implementation and timing closure of critical blocks. Silicon bring up. Proven silicon.

Architecture, micro-architecture, implementation of high speed memory PHY for DDR4/3, LPDDR4/3, HBM, SGMII, Ethernet 1000base-X. Proven silicon with 16nm and 7nm process technology.

High Speed Memory PHY Design for DDR3/4, QDR, Reduced Latency DRAM (RLDRAM). SGMII, Ethernet 1000base-X etc. RTL design and synthesis of critical blocks such as built in self calibration for VT compensation, serializers and deserializers, clock generators etc. for 16 nm FinFet Technology. Micro-architecture, RTL design and backend feasibility analysis of Network switches for Network on Chip (NOC) for FPGA. STA and timing closure at 2.1Gbps and 2.667Gbps. Software implementation of hardware to enable ASIC type design on FPGA.

High Speed Memory PHY Design for double Data Rate Synchronous Dynamic Random-Access memory(DDR2/3/4 SDRAM), NAND FLASH, Quad Data Rate SRAM(QDR), etc. RTL coding for voltage & Temperature training and tracking state machine, digital delay lines and other critical RTL blocks. Synthesis using Design Shell, Placement of designed modules using Design Shell Topographical, pre and post layout Static Timing Analysis using PrimeTime and Timing Closure of the NAND flash design at 1GHz for 28 nanometer TSMC technology. Simulation, Formal verification, lint, CDC etc.

Emulation of Obsessive Compulsive Disorder using Carbon Nanotubes, Directed Research-Alice Parker >Designed a neural network to emulate the behavior of a patient suffering from Obsessive Compulsive Disorder.>Simulated and exhaustively tested the repeated firing action suffered by the patient.