As a Lead Product Engineer at Cadence Design Systems, I am responsible for developing and supporting conformal LEC tool for logic equivalence verification. I support customers like Qualcomm, Texas Instruments and Infineon to resolve critical issues related to conformal LEC tool.I have 6.5+ years of experience in the VLSI industry, having previously worked as a SoC Design Engineer at Intel Corporation. There, I performed formal equivalence verification (FEV/LEC), low power verification (VCLP) convergence and signoff.Hands-on experience of Conformal LEC, ECO, CLP.Expert in debugging LEC run non-equivalents, aborts, and resolve high runtime issues. Involved in ECO patch generation, low power audit checks.I have a Master of Technology (M.Tech.) in Microelectronics and VLSI from Indian Institute of Technology, Kharagpur, and a Bachelor of Engineering (B.E.) in Electronics from Andhra University. I am passionate about learning new technologies and applying them to solve complex problems in the VLSI domain.