A Design Verification Engineer with 3+ years of experience of IP and subsystem level verification that includes but not limited to high speed interconnect, high bandwidth memory, FPGA blocks using advanced methodologies - UVM, SystemVerilog.In the process, I worked on both Synopsys (Verdi, DVE) and Cadence tools.As for verification process automation, I develop scripts both in python and shell.I collaborate effectively with cross-functional teams, including design engineers and system architects.