Asvin Kumar Email & Phone Number

Austin, Tx, Us

Austin, Texas, United States

Hyderabad, Telangana, India

Hyderabad, Telangana, India

Active Developer for the Deep Learning HDL ToolboxI work on enhancing the Deep Learning IP to support the hardware FPGA deployment of DL Toolbox layers. My goal is to improve the capabilities of the toolbox and to open up new workflows for customers. * I have added hardware FPGA support for the MaxUnpooling2DLayer and the TransposedConv2DLayer. * To support these layers, I created area-optimized designs while keeping timing constraints in check. * I have extensively used tools like Simulink, HDL Coder and Xilinx Vivado while working on the DL HDL Toolbox.I have also contributed to the creation of several examples showcasing the capabilities of the DL HDL product. Here's a list of the examples I have worked on:1. Bicyclist and Pedestrian Classification on an FPGA using the DL HDL Toolbox2. Semantic Segmentation using a quantized U-Net on an FPGA using the DL HDL Toolbox3. Human Pose Estimation detection on an FPGA using the DL HDL ToolboxThe DL HDL Team follows the Agile development process and I have good familiarity with its principles. I have also been thoroughly exposed to Unit Testing practices and Version Control Systems.

Hyderabad Area, India

I was a part of the Engineering Development Group (EDG) at MathWorks during this 2-year period. In this role, I juggled multiple tasks. I provided Technical Support on a monthly basis as well as worked on projects with various teams at the Hyderabad office. * I worked with the Deep Learning Toolbox team to create an initial prototype of the resize2dLayer. * Next, I worked with the Deep Learning with MATLAB Coder team to create initial prototypes for INT8 quantization of Deep Learning networks. * I finally started working with Deep Learning HDL Toolbox. I have been working with this team ever since. My other roles at EDG included leading internal teams to bring about process improvement, coaching peers on Tech Support best practices and sharing knowledge gained from working on projects.

Hyderabad, Telangana, India

Developed an HDL-Optimized design for the FPGA deployment of a Low Light Enhancement (LLE) algorithm. LLE is pre-processing step for applications in autonomous driving, scientific data capture, and general visual enhancement.My work during the summer resulted in the creation of an example in the MathWorks Docs that demonstrated the creation of HDL design using the single datatype. https://www.mathworks.com/help/visionhdl/ug/low-light-enhancement.html

Bachelor Of Technology, Electrical, Electronic And Communications Engineering

Activities and Societies: Literary Society, Nvision Online Publicity

High School, Science, 98.8%