Aswathy Narayanan Email and Phone Number

Responsible for:~ Efficient Power Delivery & Reliability Verification at full-chip for Intel P-cores.~ IP level static and dynamic IR drop analysis (Full Chip & block level), pre and post thermal analysis, signal and power EM analysis.~ Power grid design for both front-side and backside power delivery.~ Bump planning for multi-power designs.~ Power grid integrity and robustness checks across IP.~ ESD checks and verification.

~ Started the journey of being a layout owner by assisting the integration of sea of blocks design on Intel’s 10nm micro architecture, Willow-Cove.~ Further led L2 cache full chip layout in Cypress Cove, a version of the Sunny Cove microarchitecture backported to Intel's 14 nm process node.~ Led mid-level cache and power management cluster's full chip layout convergence for RedWood Cove P-Core for Intel's 7nm Meteor Lake mobile processors.~ Extensive convergence experience from leading a complex, dense and multi-voltage cluster, without compromising timing and PPA.~ Conducted STA, DRC and LVS checks to ensure tape-in quality layout.~ Collaborating with cross-site cross-functional teams was very rewarding.