Analog Design Manager for a Driver Group based out of Santa Clara. Responsible for High Voltage Gate Driver design - Including high voltage Integrated Isolated power/data transfer and non-Isolated Gate Drivers that go into a variety of Industrial/automotive applications.

Responsible for High Voltage Gate Driver design - Including high voltage Integrated Isolated power transfer and HV non-Isolated Gate Drivers that go into a variety of Industrial/automotive applications.

TPS25740/41 – USB Power Delivery and Type-C controller Design architect and analog lead for TPS2574X family devices. Includes designing new I/Ps for the BMC baseband communication AFE and circuits related to USB Type C compliance specification. Also included were the high voltage (40V) gate drivers. Analog and Mixed signal verification of the top-level functionality of TPS2574X  Assumed key responsibilities in post silicon bench evaluation, silicon debug, guiding design and system validation, performing look-ahead ESD tests, characterization and final test review, HTOL failure debug TPS25711 – USB Power Delivery (type A/B) Transmit modem design lead for USB Power Delivery product (TPS25711) – architected and designed the 23MHz transmit FSK modem. This design included the implementation of a 545MHz Phase Locked Loop, a novel clock phase multiplexing for data modulation and multiphase sine DAC driver.  Design of 3.5% reference FLL based oscillator for TPS25711 - 1.5% 6-sigma accurate frequency performance across -40 to 125C. This design has been adapted into the next generation TPS2574X devices.

1. Digital PLL Design2. Compressive Sensing Hardware Implementation3. Top-level layout and integration for mixed signal chip

Analog Circuit design in the Power Management group

 Designed and implemented an integer ratio clock divider scheme from 1:1 clock ratio onwards, derived from a source clock. Handled the full chip timing analysis using PrimeTimeTM for the low power version of the first 90nm Blackfin DSP IC (BF 52x). Added feature enhancements to serial and parallel communication peripherals used for all 65nm BlackFinTM DSP ICs in the roadmap.  Clock Skew Balancing, Power Optimization and Clock domain crossing issues related with synchronizers.  Circuit level simulations on reference design blocks in 65nm and 90nm processes to decide on the type and ratio of transistors (High Vt to Low Vt) Working knowledge in CadenceTM VirtuosoTM, SynopsysTM PrimetimeTM, HSPICETM, NanosimTM, Verilog RTL designing, PerlTM and shell scripting.