Asya Thomas Email & Phone Number

Good understanding of the ASIC and FPGA design flow.Experience in writing RTL models in Verilog HDL and Testbenches in System Verilog.Very good knowledge of verification methodologies, especially in UVM.Knowledge in protocols like SPI, QSPI, AXI4, AXI4-Lite, APB, LPDDR4, MIPI CSI, and MIPI DSI.VLSI DOMAIN SKILLSHDL: VerilogHVL: System VerilogTB Methodology: UVMEDA Tool: Questasim, Modelsim, Xcelium, Synopsys VCS, Xilinx Vivado, and Xilinx ISE design suiteDebugger Tool: Xilinx ChipScope Pro, Intel-FPGA signal TapRevision Control Tool: GitHub, GitLab, MercurialDomain: ASIC/FPGA Design, Digital Design methodologies, UVM VerificationKnowledge: RTL Coding, FSM based design, Simulation, UVM based Verification, System Verilog Test bench development, IP integration and Verification, Python scripting, Algorithm validation

Listed skills include Matlab, Python, Microsoft Office, Micro Processor, and 12 others.