Digital Design Fpga Engineer
Current• Developed FPGA design on Versal SoC using Linux-based development tools (Yocto, Petalinux) to program and integrate solutions for reliable aerospace and defense applications.• Collaborated closely with software teams to integrate UART with the Versal SoC, contributing to the development of drivers in Petalinux and verification of register reads/writes using freeRTOS on an ARM A72 processor.• Experience developing FPGAs (Versal, Polarfire) for aerospace defense applications. Designed FPGA top-level architecture, wrote code, conducted timing analysis, and validated SPI, UART, SGMII, PCIe, and MRMAC modules within a Versal SoC FPGA.• Gained experience in reading PCB schematics, technical documents, and customer requirements through the design and development of Preliminary Design Review (PDR) and Intermediate Design Review (IDR) processes.• Utilized shell scripting extensively to automate build processes, improving efficiency in development workflows.• Mentored and supervised an intern in FPGA development, providing guidance on project tasks and conducting regular check-ins to monitor progress.• Wrote and verified a UART module, conducting initial functional verification with simulation tools.• Collaborated with the software team to integrate UART module onto a Versal SoC using Petalinux; developed a UART driver after initial verification of register reads and writes using freeRTOS.• Led a project to bridge FPGA and software development by creating automating device tree generation using a DDR3hard macro in the Versal SoC as a reference, integrated with a Yocto-based Linux OS.• Developed a reusable, parameterized Verilog wrapper for Xilinx 10/25/50/100G Ethernet MRMAC IP.• Used SVN for revision control of RTL designs and Git for software development version control.• Developed Python automation scripts to convert .bif files into AES and ECDSA-encrypted secure files, automating Root of Trust boot processes and ensuring secure system startups.
