Lokesh Avala Email & Phone Number

Bengaluru, KA, IN

Bangalore Urban, Karnataka, India

- Patent Drafting (IN, US, EP) in Electronics, Electrical, Mechanical, and Software domains.- Preparing responses to Examination Reports (IN) and Office Actions (US and EP).- Conducting patentability searches/studies.- Interacting with clients to understand the invention and review disclosures for patentability.

Endicott, NY

• Created Manual verification tests for and manually tested Actuator Controller Electronics(ACE) Normal Mode(NM) to be applied in Boeing 777X airplane.
• Was responsible to maintain/debug Universal Test Stand(Customized UTS) at clients location for offshore team.
• Performed regression testing when needed for NM automated(offshore) team located in India.
• Trained two interns to be able to understand and get involved in NM Manual test.

Tempe, AZ

• Worked alongside Senior Test Engineer and supported in conversion of production test program(s) from LTX to SPEA C600MX Mixed Signal IC (SPEA).
• Participated actively in verification and validation of LINQ2 Hybrid test program on SPEA tester to quicken the release process.
• Worked towards release of updated test program for LINQ on SPEA tester to improve yields at IC wafer level.
• Performed set-up, calibration, testing and troubleshooting of HW(Load boards, Probe cards etc) and test programs used in production on SPEA testers.
• Created Test plans and reports after performing Equivalency and R&R study to release HW for production use.
• Performed data analysis using test analysis tools like Spotfire and Pacekeeper.

Dallas

• Graduate Research Assistant Jan 2015 - May 2017
• Was solely responsible to design, layout and tape-out of 3*3mm complete chip consisting of DC regulation circuit as well as two transceivers for Up-Link(915MHz) and Down-Link(2.4GHz) in 130nm CMOS process.
• Designed a 250mV low input voltage rectifier with dual DC boost with generated DC voltage output of 450mV and ~110mA current.
• Designed and implemented two coil shaped antenna’s(simulated in HFSS) with dimensions 1cm*1cm and 4cm*4cm on PCB and designed 400MHz rectifier and LDO regulator in 130nm CMOS process to implement inductive coupling.
• Participated in layout design and tape-out of Multi-Band RF transceiver and serial link in GF 65nm CMOS process and for RF transceiver, QVCO and injection locked frequency divider(ILFD) in TI65nm CMOS process.
• Graduate Teaching Assistant Jan 2015 - Dec 2016

Morgantown, WV

• A low power 22GHz transceiver with on-chip Dipole antenna(simulated in ADS) was designed and fabricated in IBM 180nm CMOS process.
• Designed a dual gm-boosted LNA with a wide frequency range of 100MHz to 800MHz.

Master'S Degree

Excutive Diploma

Master'S Degree

Bachelor'S Degree

Higher Secondary Education