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Avanee Bhat M V Email & Phone Number

Senior Silicon Design Engineer at AMD
Location: Santa Clara, California, United States 8 work roles 2 schools
1 work email found @amd.com LinkedIn matched
4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email a****@amd.com
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Current company
AMD
Role
Senior Silicon Design Engineer
Location
Santa Clara, California, United States
Company size
44382 employees

Who is Avanee Bhat M V? Overview

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Quick answer

Avanee Bhat M V is listed as Senior Silicon Design Engineer at AMD, a company with 44382 employees, based in Santa Clara, California, United States. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Avanee Bhat M V.

Avanee Bhat M V previously worked as Member of Technical Staff (CPU Verification) at Amd and Graphics Hardware Debug and Validation Engineer at Intel Corporation. Avanee Bhat M V holds Master Of Science (Ms), Electrical Engineering from University Of Southern California.

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Email format at AMD

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*@amd.com
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AeroLeads found 1 current-domain work email signal for Avanee Bhat M V. Compare company email patterns before reaching out.

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Profile bio

About Avanee Bhat M V

Experienced technical professional with a cross functional background in post silicon validation as well as pre silicon functional verification. Currently working on AMD Cores and previously worked on Intel GPUs. Committed to ensuring the correctness and functionality of digital systems. Experience with Logic Analyzers, Oscilloscopes. Semiconductor Design/Verification Tools: ModelSim, QuestaSim, Cadence Virtuoso, HSpice, Altera Quartus FPGA, NCSim, Design Compiler, Synopsys Prime Time, Cadence Encounter, Cadence ConformalProgramming Skills: Verilog, System Verilog (UVM), C, Perl, Python, shell, x86 Assembly Level programmingOperating Systems: Windows, Linux, Mac OS, Ubuntu

Listed skills include Leadership, Six Sigma, Altera Quartus, Logic Design, and 40 others.

Current workplace

Avanee Bhat M V's current company

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AMD
Amd
Senior Silicon Design Engineer
Santa Clara, CA, US
Website
amd.com
Employees
44382
AeroLeads page
Company profile
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8 roles

Avanee Bhat M V work experience

A career timeline built from the work history available for this profile.

Senior Silicon Design Engineer

Amd

Santa Clara, CA, US

Member Of Technical Staff (Cpu Verification)

Current
Amd

Santa Clara, California, US

CPU Core Level Verification - Responsibilities include Testplanning, uarch feature bring up, x86 feature enablement, stimulus development, debug and coverage closure for both Architectural and Micro Architectural features.

Feb 2020 - Present

Graphics Hardware Debug And Validation Engineer

Intel Corporation

Santa Clara, California, US

- Debug and validation of Intel's GPU on Intel’s client/customer platforms. (Post Si)- Involved in Silicon bring up activities and tape in gating debugs. Our team is also the last line of defense before the declaration of Product Release with the intent to catch as many RTL bug escapes as possible while also meeting a highly aggressive release time frame..

May 2017 - Feb 2020

Mentor For Vlsi System Design Ii (Ee577B)

University Of Southern California

Los Angeles, CA, US

Responsible for designing Lab, Homework Assignments and Projects.Assisting students by clearing doubts related to VLSI System Design.Also helped design solutions for homeworks and Labs

Aug 2016 - Dec 2016

Student Technical Lead

Usc Information And Technology Services- Learning Environments

I lead a team that works together to ensure the smooth functioning of classes within a short period of time. Provide technical support and help resolve issues related to smart classrooms, computing centers and auditoriums where customer satisfaction is the key focus. I also mentor new hires on standard protocols of ITS-LE and troubleshooting techniques.

Dec 2015 - Dec 2016

Viterbi Graduate Mentor

Usc Viterbi School Of Engineering

Los Angeles, California, US

Viterbi Mentorship program is designed to help new international graduate students adjust quickly to life at USC by pairing new students with current Viterbi graduate students. We meet on a regular basis and I help them make a smooth transition from the difference in culture in their home country to a new country.

Dec 2015 - Dec 2016

Student Technical Assistant

Usc Information And Technology Services-Learning Environments

Responsible to interact with professors that teach on campus to provide technical support for technology- enhanced classrooms and computing centers. Ensuring customer satisfaction without any class time being affected remains the primary objective along with skilled troubleshooting of projector and printer issues.

Jul 2015 - Dec 2015

Summer Intern

Hindustan Aeronautics Limited

IN

Went through a rigorous in-plant- internship training in Hindustan Aeronautical Ltd (HAL).Exposed me to CAD (Tool Design), CAD/CAM manufacture, CNC, CATIA, and 5 Axis Special Purpose CNC Machining Centers. Learnt how accelerometers, gyroscopes, microprocessor based displayand sighting systems are incorporated in the Avionics dept.

Jun 2013 - Jul 2013
Team & coworkers

Colleagues at AMD

Other employees you can reach at amd.com. View company contacts for 44382 employees →

CW Ching Weng-Yin Ching Weng-Yin Colleague at Amd Penang, Malaysia, Malaysia View → KD Krishna Dheeraj Putrevu Krishna Dheeraj Putrevu Colleague at Amd San Diego, California, United States, United States View → BP Bhasker Pinninti Bhasker Pinninti Colleague at Amd San Jose, California, United States, United States View → OT Omoyeni Titilayo Meg Omoyeni Titilayo Meg Colleague at Amd Lagos, Lagos State, Nigeria, Nigeria View → JF John Fedak Iv John Fedak Iv Colleague at Amd Longmont, Colorado, United States, United States View → SA Sai Anudeep Polisetti Sai Anudeep Polisetti Colleague at Amd Andhra Pradesh, India, India View → RM Ramesh Mantha Ramesh Mantha Colleague at Amd Greater Seattle Area, United States, United States View → TR Tanweer Raza Tanweer Raza Colleague at Amd Kuwait, Kuwait View → JR Juan Romo Juan Romo Colleague at Amd Salamanca, Guanajuato, Mexico, Mexico View → AJ Aarushi Jain Aarushi Jain Colleague at Amd United States, United States View →
2 education records

Avanee Bhat M V education

Master Of Science (Ms), Electrical Engineering

University Of Southern California

Bachelor Of Engineering (B.E.), Electronics And Communication Engineering

Nitte Meenakshi Institute Of Technology
FAQ

Frequently asked questions about Avanee Bhat M V

Quick answers generated from the profile data available on this page.

What company does Avanee Bhat M V work for?

Avanee Bhat M V works for AMD.

What is Avanee Bhat M V's role at AMD?

Avanee Bhat M V is listed as Senior Silicon Design Engineer at AMD.

What is Avanee Bhat M V's email address?

AeroLeads has found 1 work email signal at @amd.com for Avanee Bhat M V at AMD.

Where is Avanee Bhat M V based?

Avanee Bhat M V is based in Santa Clara, California, United States while working with AMD.

What companies has Avanee Bhat M V worked for?

Avanee Bhat M V has worked for Amd, Intel Corporation, University Of Southern California, Usc Information And Technology Services- Learning Environments, and Usc Viterbi School Of Engineering.

Who are Avanee Bhat M V's colleagues at AMD?

Avanee Bhat M V's colleagues at AMD include Ching Weng-Yin, Krishna Dheeraj Putrevu, Bhasker Pinninti, Omoyeni Titilayo Meg, and John Fedak Iv.

How can I contact Avanee Bhat M V?

You can use AeroLeads to view verified contact signals for Avanee Bhat M V at AMD, including work email, phone, and LinkedIn data when available.

What schools did Avanee Bhat M V attend?

Avanee Bhat M V holds Master Of Science (Ms), Electrical Engineering from University Of Southern California.

What skills is Avanee Bhat M V known for?

Avanee Bhat M V is listed with skills including Leadership, Six Sigma, Altera Quartus, Logic Design, Cadence Virtuoso, Questa Sim, Computer Architecture, and Test Planning.

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