Design & Implementation of 10 GigEVision and CoaXPress (12.5Gbps) frame grabber using Xilinx UltraScale+ FPGA. Design of credit based high speed memory arbiter. Integrating SLVS-EC Sony sensor Interface on Intel Cyclone 10 FPGA. Design of Multi Input Frame Buffer for multiple cameras in single FPGA.Development of CoaXPress 2.1 (12.5Gbps) IP core.Implementation of 10 Gigabit Ethernet (USXGMII).Customer specific project development.General FPGA library development.Sensor pixel sorting in camera firmware.

Design of high speed data acquisition system from large pixel detector using 20xVirtex5 FPGA's having 32x10Gbps interfaces, including modeling, implementation, synthesis, verification and testing.Organizing workshops and meetings for EUCALL (EU Horizon 2020 project) in collaboration with FEL’s of Europe and Laserlab Europe.

See Front 3D solution: A system designed for single viewer, which enables to see three dimensional images without spectacles.Real-time image acquisition from multiple HDMI based cameras and transmission to embedded computer over PCIE using Xilinx Artix 7 FPGA device.Artix 7, PCIe, HDMI FPGA Developments.

Intel Data Plane Development Kit.Software base high speed Packet processing.

Accomplished wide array of tasks related to hardware design such as requirement gathering, translating those requirements into a digital hardware design, describing the required hardware using the HDL, creating test benches and running design simulations, synthesizing and implementing the design, finally testing the design on actual hardware.Network Monitoring SystemThe data is collected from multiple 10Gbps links on CX4/fiber interface, then deep packet protocol analysis is performed. The project was acomplished by using Xilinx virtex5 FPGAs.10Gbps Ethernet MACImplemented 10Gbps Ethernet MAC core utilizing XAUI corePCIE and DMAPCIE and DMA has been implemented for Xilinx Virtex-5 boards.String Matching Core The core was designed and developed to perform exact string matching on live network traffic at 5Gbps.Webserver Implementation on MicroblazeWebserver was integrated with Network Monitoring System for configuring filters, inputs and outputs.NVIDIA CUDAImplementation of Aho-Corasik Algorithm for Exact String Matching for DPI at live 5Gbps traffic.Embedded LinuxLink Aggregation and Load Balancing of Internet traffic using linux Distro.URL Blocking SystemImplemented URL Compression and Fast Searching for URL Blocking System