Ayush Dixit Email and Phone Number
Hi, I'm Ayush, a passionate and dedicated professional with a strong background in semiconductor design, verification/validation(Silicon Bring-Up planning) and Hardware engineering.🔌 My expertise lies in the fascinating realm of pre-silicon verification and post-silicon validation. With a proven track record of successfully ensuring the functionality and reliability of complex IP designs, I thrive on the challenges that come with pushing the boundaries of innovation. On LPDDR 3/4/5 and Gen 4/5 (3nm💡I also possess a comprehensive grasp of software engineering encompassing cutting-edge fields like machine learning and AI, all within the context of the semiconductor domain.💡 As a firm believer in the power of code to drive innovation, I'm adept at coding in Python and other software languages. I leverage this skill to create efficient automation solutions, streamline processes, and enhance productivity. My ability to bridge the gap between hardware and software enables me to contribute effectively to projects that require a well-rounded perspective.🚀 Beyond my professional pursuits, I'm an avid learner, writer and a blogger, always seeking opportunities to broaden my knowledge and stay up-to-date with the latest industry trends. I'm excited about the future of technology and the incredible possibilities it holds.📌 PROFESSIONAL SKILLS:→ System Verilog/UVM→ C/Embedded C→ Python→ Machine Learning/Deep Learning→ Product management→ Verbal and presentation skills🧑🏫 HOBBIES:→ Writing & Blogging→ Gym → Traveling→ Teaching🏆 Top 5 Achievements:→ 10+ Cerifications on Course Era and Udemy→ Hacker Rank Python Gold Badge→ GATE AIR : 532 (ECE)→ Highest Score for Masters Thesis on "Optimizing Random Verification in Modem Sub-Systems using Machine Learning"→ Technical Blog posts featured in leading tech publications on Medium📬 If you're interested in connecting, collaborating, or simply sharing insights, feel free to reach out. Let's engage in meaningful conversations and explore how we can make a positive impact on the world through technology.Email id : ayushdixit777@gmail.com Website : ayushdixit.comTechnical Blog : https://medium.com/@ayush_dixitThank you for visiting my profile, and I look forward to connecting with you!**DISCLAIMER: All activity on this platform represents solely my own opinions and is not in any way, shape, or form, a representation of my current or past employers **
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Lead Validation EngineerNxp Semiconductors Nov 2024 - PresentNoidaResearch & Development - Functional Validation -
Post Silicon Validation EngineerQualcomm Jun 2021 - Nov 2024Silicon Validation Engineer - DDR Subsystem and Mixed Signal Systems (MS-SVE)-- Part of the Post Silicon DDR-PHY Bring-up Team (Design and Validation)-- Required to create, define and develop system validation environment & test suites optimized for a CPU, DDR or its subsystems like memory controller, PHY(Physical Layer) and other modules of given complexity. -- I am responsible for the development of test plans, execution of validation plans/ coverage, and debug of failures. -- My work requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features. --Understanding and debugging legacy codes in C and C++ for different MSM's/projects concerning DDR-PHY Bring-up.☛ Silicon Validation‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾ ● Work on the latest LPDDR technologies (LPDDR4, 4x, 5, 5x) across varied platforms of Mobile, Auto, Compute and IoT chipsets.● Work on Oscilloscopes and Data eyes for electrical and functional validation of DDR-PHY● Own and maintain DDR Firmware (C language) to tune key parameters for high-speed communication on LPDDR protocol. Validate DDRPHY block with the help of DDR Firmware over JTAG interface using Lauterbach Trace32.● In Post-Silicon, work with key stakeholders in VI, ATE, Bench and Software teams for successful Bring-Up of DDRPHY block, from SoD to CS.● Make sure timing, voltage and other parameters match with the official JEDEC specs.● Work with Design and DV during Pre-Silicon timeline to understand design changes / features to validate on Silicon.☛ Programming / Tool Development‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾● Bring-Up new APIs for DDR Training in C language.● Linux Shell scripting for automation and makefile customizations.● Python scripting for Volume Data analysis, CSV file optimizations and automating Post-Si experiments for triage. -
Interim Engineering Intern : Pre-Silicon VerificationQualcomm Jul 2020 - May 2021-- Pre-Silicon Verification-- Designing an Artificial Neural Network to optimise Random Verification. -- Implementation of Machine Learning in the Design/Verification environmement. -- Working on Verification methodologies, architecture, and UVM constructs to build scalable and reusable verification collaterals. -- Collaborate with the design teams to develop robust verification strategy, defining test plans, test writing, and debug in accordance with IP spec. -- Pre-Silicon Verification
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Placement CoordinatorIit Indore Training And Placement Cell Sep 2019 - Apr 2021
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Subject Matter ExpertSkill Planet Dec 2019 - Dec 2020Handling projects involving UI/UX, Verilog, Software development cycle, protocol stacks, Embedded C and Telecom BSS. -
Teaching AssistantIndian Institute Of Technology, Indore May 2019 - Jul 2020Indore, Madhya Pradesh, IndiaM.Tech - Communication, signal processing and AI -
Assistant EngineerEricsson Oct 2015 - May 2017Gurgaon, Haryana, IndiaMPBN/RAN Engineer -: 2nd LA Back Office• Dealt with monitoring tools like network packet capture tools like Wire-shark, cisco packet tracer etc.• Troubleshooting both the voice and data over ip technologies environment.• Replacing branch hardware with new 2851 routers and 2960 switches.• Performing security audits of perimeter routers, identifying missing ACL’s• Troubleshooting of complex LAN/WAN infrastructure, including routing protocols EIGRP, OSPF & BGP. -
Content CreatorThankship Jan 2016 - Jun 2016London, United KingdomContent Writing for featured articles on Thankship.com. Great intiative which fosters gratitude in the corporate and social sector. -
Project Intern(Embedded Electronics)Texas Instruments Jan 2015 - Mar 2015New Delhi Area, India -
Campus Recruitment AmbassadorThinnkware Jul 2014 - Jan 2015Greater Noida
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General SecretaryGnix(Electronics Society Of Gcet) Aug 2013 - Aug 2014Galgotia College Of Engineering And TechnologyHeaded the technical society of Galgotias Educational Institutions. To know more about Gnix check out the fb page-: http://goo.gl/Hs9Pt7And the slideshow-:http://goo.gl/CUwvgk
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Campus AmbassadorPristine Info Solutions May 2013 - Jun 2014Noida Area, India
Ayush Dixit Education Details
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95.37 % -
Galgotia College Of Engineering And TechnologyElectronics And Communication -
Cms Gomtinagar
Frequently Asked Questions about Ayush Dixit
What company does Ayush Dixit work for?
Ayush Dixit works for Nxp Semiconductors
What is Ayush Dixit's role at the current company?
Ayush Dixit's current role is Lead Validation Engineer @ NXP | Ex-Qualcomm | Ex-Ericsson | IIT Indore | LinkedIn Top Voice.
What schools did Ayush Dixit attend?
Ayush Dixit attended Indian Institute Of Technology, Indore, Indian School Of Business, Galgotia College Of Engineering And Technology, Cms Gomtinagar.
Who are Ayush Dixit's colleagues?
Ayush Dixit's colleagues are Ramona Anghel, Hugo Cedeno Rojas, Vishwajit Bugade, August Nothnagel, Ariel Ty, Gudrun Goeldner, Gandharva Akula.
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