Ayush Dixit Email & Phone Number

Noida

Research & Development - Functional Validation

Silicon Validation Engineer - DDR Subsystem and Mixed Signal Systems (MS-SVE)-- Part of the Post Silicon DDR-PHY Bring-up Team (Design and Validation)-- Required to create, define and develop system validation environment & test suites optimized for a CPU, DDR or its subsystems like memory controller, PHY(Physical Layer) and other modules of given complexity. -- I am responsible for the development of test plans, execution of validation plans/ coverage, and debug of failures. -- My work requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features. --Understanding and debugging legacy codes in C and C++ for different MSM's/projects concerning DDR-PHY Bring-up.☛ Silicon Validation‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾ ● Work on the latest LPDDR technologies (LPDDR4, 4x, 5, 5x) across varied platforms of Mobile, Auto, Compute and IoT chipsets.● Work on Oscilloscopes and Data eyes for electrical and functional validation of DDR-PHY● Own and maintain DDR Firmware (C language) to tune key parameters for high-speed communication on LPDDR protocol. Validate DDRPHY block with the help of DDR Firmware over JTAG interface using Lauterbach Trace32.● In Post-Silicon, work with key stakeholders in VI, ATE, Bench and Software teams for successful Bring-Up of DDRPHY block, from SoD to CS.● Make sure timing, voltage and other parameters match with the official JEDEC specs.● Work with Design and DV during Pre-Silicon timeline to understand design changes / features to validate on Silicon.☛ Programming / Tool Development‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾● Bring-Up new APIs for DDR Training in C language.● Linux Shell scripting for automation and makefile customizations.● Python scripting for Volume Data analysis, CSV file optimizations and automating Post-Si experiments for triage.

-- Pre-Silicon Verification-- Designing an Artificial Neural Network to optimise Random Verification. -- Implementation of Machine Learning in the Design/Verification environmement. -- Working on Verification methodologies, architecture, and UVM constructs to build scalable and reusable verification collaterals. -- Collaborate with the design teams to develop robust verification strategy, defining test plans, test writing, and debug in accordance with IP spec. -- Pre-Silicon Verification

Handling projects involving UI/UX, Verilog, Software development cycle, protocol stacks, Embedded C and Telecom BSS.

Indore, Madhya Pradesh, India

M.Tech - Communication, signal processing and AI

Gurgaon, Haryana, India

MPBN/RAN Engineer -: 2nd LA Back Office• Dealt with monitoring tools like network packet capture tools like Wire-shark, cisco packet tracer etc.• Troubleshooting both the voice and data over ip technologies environment.• Replacing branch hardware with new 2851 routers and 2960 switches.• Performing security audits of perimeter routers, identifying missing ACL’s• Troubleshooting of complex LAN/WAN infrastructure, including routing protocols EIGRP, OSPF & BGP.

London, United Kingdom

Content Writing for featured articles on Thankship.com. Great intiative which fosters gratitude in the corporate and social sector.

New Delhi Area, India

Greater Noida

Galgotia College Of Engineering And Technology

Headed the technical society of Galgotias Educational Institutions. To know more about Gnix check out the fb page-: http://goo.gl/Hs9Pt7And the slideshow-:http://goo.gl/CUwvgk

Noida Area, India

Master Of Technology - Mtech, Communication-Signal Processing And Ml-Ai(Machine Learning - Artificial Intelligence), 8.7/10

Activities and Societies: Thesis : Optimizing Random Verification in Modem Sub-Systems using Machine Learning

Product Management, 95.37 %

Bachelor Of Technology (B.Tech.), Electronics And Communication

Education record