13+ years of experienceAnalog Circuit design experience of PLL,CDR, Transmitter, Receiver and SerDes.IBIS3.2 generation and verification, Reliability analysis for sub-micron technology designPHY level integration and Verification using the verilog model, Create the verilog model for the analog design and integrate with the existing test env for the verificationPHY analog domain architect based on the spec and behavioral model availabilityCustomer support in pre and… Show more 13+ years of experienceAnalog Circuit design experience of PLL,CDR, Transmitter, Receiver and SerDes.IBIS3.2 generation and verification, Reliability analysis for sub-micron technology designPHY level integration and Verification using the verilog model, Create the verilog model for the analog design and integrate with the existing test env for the verificationPHY analog domain architect based on the spec and behavioral model availabilityCustomer support in pre and post silicon levelPre-sale technical discussionWork with layout team to optimize the layout for meeting the requirements and initial level floorplanning Work with digital designers for the PHY verificationDesign MIPI CPHY, DPHY and MPHY analog designDesign JEDEC eMMC51 IOs and xSPI IOsDesign UHS2 PHY analog designDesign USB2.0 PHY analog design for data transfer portionManage/lead the PHY development activity Show less