- Develop and maintain the R-Tile FPGA software compilation flow, enhancing the RTL integration process in the Intel Quartus software through the use of C/C++, Python, Makefile, and Perl.- Develop and maintain software simulation model written in System Verilog & Verilog for Intel Transceiver tile which consist of PCIE, Compute Express Link, Ethernet and other various IP.

Develop a mobile application based on IP communication protocol using a ReactNative framework.

STUDIES OF FPGA COMPONENTS + ACQUISITION ON PC-FPGA integration of user logic configurable on pulses from photon detectors.-Integration of photon counting for frequencies above 100MHz on a low cost FPGA card.