• System level Signal Integrity (SI) closure for high speed Interfaces (HSI) such as USB2, USB3, SATA, PCIE, HDMI Electrical Modeling of Package/PCB and extraction of power/signal nets System level SPICE simulations for timing closure as per interface compliance specifications• Power Integrity (PI) closure for multiple voltage domains at Package/PCB (P-G Networks) Static/Dynamic IR drop on Die, Package and PCB power/ground• Die-Package Physical Design implementation BumpPlanning, IORing creation/placements, Ball-pin Assignment, Analog Macro Placement• Daisy Chain test vehicle development for board level reliability and thermal testing on Package • Physical verification closure - ESD, Package-DRC, Metal-DRC, LEC• Worked on different Package ICs types such as Flip Chip, WireBond, Package-on-Package and Chip Scale CU Pillar designs