Custom circuit design and verification for compute-in-memory.

Under the guidance of Prof. Janakiraman Viraraghavan:-1. Design and layout of an in-memory compute engine (custom SRAM memory ~400Kb, pitch-matched programmable Currents Mirrors with analog calibration, 2Bit DAC as RWL driver with custom SRAM Input Buffer). Chip 2023 TSMC 28nm2. I participated in designing and layout of word line drivers (digital to analog converters)- Chip 2020 TSMC 28nm.3. Proposed an area-efficient in-memory compatible DAC as presented in ISCAS 2021.

Coordinated and organised music club events for virtual Saarang 2021 and helped in establishing a social media presence for the club.

1. Layer-wise and system-level simulation of a novel In-memory compute technique to implement MLP on IMC ( In memory compute) hardware for MNIST.2. Was exposed to SRAM and Sense amplifier layout design so as to ensure DRC and LVS error-free layouts.

1. Designed an optimally quantized image classification neural network that aims to strike a balance between classification accuracy and hardware resource usage.2. Developed a behavioural Verilog module that serially implements the computations involved in the neural network.

1. Developed a real-time kitchen inventory tracking system prototype. The system aimed at identifying weight changes to inventory items and notifying the end-user. 2. Researched on techniques to uniquely identify various inventory items irrespective of their physical location in the chamber.