Balaji Siruvaram Email & Phone Number

Performance driven & dedicated trainee with an extensive logical approach skills in VLSI domain & HDL programming along with Hands-on experience on VLSI projects.UVM | FACORY | TLM | PHASES | SYSTEM VERILOG| OOPS | CRCDV | FUNCTIONAL COVERAGE| ARRAYS | VERILOG | SYNTHESIZABLE CONSTRUCTS | DIGITAL DESIGNBEHAVIORAL SKILLS-> Team player-> Problem solving-> Effective communicatorACHIEVEMENTS-> Cleared GATE examination consecutively in 2021 & 2022.-> Consecutively 5 times STAR OF THE MONTH in Maven Silicon.Completed a mini project called 4*4 Vedic multiplier during internship in ECIL,Hyderabad.This is the place where the seed of interest in VLSI has been sowed into my life.PROJECTS -> ROUTER 1*3HDL:- Verilog HVL:- System VerilogMETHODOLOGY:- UVM Methodology