Barry K Britton Email & Phone Number

Chandler, Az, Us

Aliso Viejo, Ca, Us

Responsible for technical development and management of ASIC and FPGA products. • Managed a ~60 person team located internationally developing RTG4 radiation-tolerance based ITAR space FPGA product. Developed radiation requirements and developed new rad-hard by design ASIC flow.• Directed an organization that owns the development of the RTL-based design flow and embedded RTL-based blocks, 500 Mb/s to 12.7 Gb/s SERDES and PLLs purchased IP cores and internally developed 1600 Mb/s IO sub-systems for 65 nm (RTG4 FPGAs), 28 nm (PolarFire FPGAs) and more advanced process nodes. Team owns key capabilities from definition to implementation stages and support during validation stages.• Technical Proposal and Implementation Leader for US government projects. Includes ASIC and FPGA projects using 22 nm FinFet and other advanced integrated circuit process nodes.• Additional responsibilities include site management of the Allentown, PA facility for the MIcrosemi SOC division, Program technical management for US Government contracts, Technical Interface to Intel for Advanced 22 nm process integration, and Customer Technical Proposal Development for ASIC development projects.

Hillsboro, Oregon, Us

After acquisition of the Agere Systems embedded FPGA team, named site director for the PA location with site budget ownership. Directed facilities, IT, HR, R&D, Product Planning, Marketing and Applications.• Managed through business growth and recession. Site employees rose from 65 to 90 employees, then reduced to 60 before again growing by hiring direct employees and on-site/off-site contractors• Directed the specification of multiple embedded FPGA and IP products including large portions of major product lines such as the SC, XO and ECP FPGA product lines that are currently in production

Hillsboro, Oregon, Us

2008-2011: During a function-aligned company re-organization in 2008, assumed increased responsibility as the Director of Embedded Design. Also performed work in the CTO organization investigating 28 nm technologies• Owner of mixed signal and “RTL” based development with employees in 3 US development sites and one site in Shanghai, China. Led development of very low power mixed signal blocks and RTL system control and configuration blocks for a device that decreased static ICC by > 1000x vs. previous devices• Project owner for two of the three major hardware planning and development activities (FPGA, power management) while also participating in the third major project for Lattice (separate FPGA project)2005-2008: During a project-aligned company re-organization in 2005, assumed increased responsibility as the owner for one of two hardware development project teams at Lattice with employees in two sites.• Developed new FPGA architectures and test chips with a target of 65 nm and 40 nm process technologies. The test chips included low power techniques and >6 Gb/s SERDES circuits2002-2005: After the acquisition, directed development of FPGA and Embedded FPGA device families (also known as Field Programmable System Chips – FPSCs) with targets to 0.16 um and 90 nm fabs.• Managed R&D, marketing, product planning, and applications teams with direct customer interactions during the definition of future company products and in support of current products• Directly interacted with all Lattice teams to integrate the key capabilities obtained via the acquisition• Key technical contributor in the acquisition of a SERDES development team for Lattice and was a key participant in the specifications for integrating SERDES onto future devices

2001-2002: R&D Director, Field Programmable Gate Arrays Hardware DevelopmentResponsible for product planning and silicon hardware development of all Agere Systems FPGAs and FPSCs, including the ORCA Series 4 FPGAs and FPSCs. • Lead technical interface to multiple potential buyers of the FPGA/FPSC business from Agere Systems (sold to Lattice Semiconductor for $250M) based on annual revenue of $157M.• Developed the first embedded FPGAs in the industry with 2.5 Gb/s and 3.3 Gb/s SERDES/PCS2000-2001: Strategic Marketing Sr. Manager, Network Communications (Netcom) Core GroupResponsible for revenue, design wins, gross margin and product roadmap for Netcom Core team. Year 2000 revenue responsibility was over $200M. 1998-2000: System Architecture Senior Manager, Broadband Network CommunicationsManaged two groups of employees to drive system architecture and technical product features for broadband optical networking solutions, including SONET/SDH, Ethernet, FPGA and ASIC products. Definition and development of 2.5 Gb/s and 10 Gb/s optical networking products• Architected the first FPGAs in the industry with embedded 622 Mb/s SERDES and ASIC blocks1994-1998: Strategic Marketing and Product Planning Manager, FPGAs and FPSCsProduct planning of ORCA FPGA hardware, software and intellectual property products.1990-1994: Member of Technical Staff, Bell Labs R&D for FPGAsPrimary architect for multiple FPGA families including the very successful ORCA family of FPGA devices.• Converted a second-source FPGA (Xilinx 3000 Series) to AT&T fabs including circuit design, packaging, testing and customer support. Family lifetime revenue $150M• Lead architect for ORCA FPGAs. Logic/circuit design, modeling, packaging, testing, manufacturing introduction, and software team interface. 1998-1990: Standard Cell ASIC DesignerBack-end circuit design of standard cell ASICs for multiple customers.

Melbourne, Florida, Us

Design and verification engineer on semiconductor, board level and firmware projects.• Design of multiple blocks, followed by full chip verification and floor-planning of a fault-tolerant RISC processor• Primary designer of a signal processing board based on MIPs R2000 RISC processor and first Xilinx FPGA family. Also developed signal processing assembly language code for the RISC processors.

M.S. Electrical Engineering

B. S. Electrical Engineering, Electrical And Electronics Engineering