Bart Wu Email & Phone Number

San Jose, CA

• One person designed the whole RF frequency synthesizer 55nm IPs for the WiFi 11ac & 11n products, including the crystal oscillator, PLL, and VCO. o System specification, frequency plan, optimization on phase noise and.
• 2G/3G/LTE RF frequency synthesizer and LO chain design, and lab bring up.o Reduced phase noise and spurs, reduced the settling time in TDD mode, improved noise isolation, and improved the pulling effect.
• ADPLL research & development: fine resolution TDC, DTC, DCO, true Fractional-N Frequency Divider.
• ADPLL new system topologies research: DTC-assisted, TDC_less, divider_less, SDM_less DCO.
• 25% duty cycle Lo Generator and LO distribution in Ultra-Low Power RF Transceiver Product Line.
• 6GHz 4-to-8 phase Lo generator with phase interpolator (PI).

Cupertino, CA

• One person in charge of the WiFi RF Frequency Synthesizers design and testing for all 0.35um/0.18um/90nm/55nm products for 9 years. Over 100 customers, from Start-up to IPO.o One person designed the whole Fractional-N.
• ADPLL (all-digital PLL) research & development: fine resolution TDC (time-to-digital converter).
• Ultra low noise charge-pump.
• Frequency Doubler and Programmable Duty Cycle Detector & Calibration.
• Sigma-Delta modulator for Fractional-N PLL and non-Sigma-Delta Fractional-N PLL.
• 10b 60MS & 120MS DAC for WiFi Baseband (90nm, 0.18um, 0.25um).

Milpitas, CA

Analog and mixed signal circuits design, including ADC, DAC, OpAmp, Comparator, Voltage Regulator, and Bandgap.

Fremont, CA

• PLL-based Clock Generator (20MHz input reference, 400MHz ring oscillator VCO), Crystal Oscillator, Frequency Dividers (divided by 2, 2.5, 3, 3.5, 4, 5, 6), and clock distribution.
• 1MB 1.5V Asynchronous SRAM.
• I/O pad (2.5V/3.3V, 5V tolerance)