Basanth Jagannathan Email & Phone Number

Shrub Oak, NY, US

- 3/2nm foundry silicon technology (finfet, nanosheet, frontside/backside power), design and partnership with mutiple foundries. - 3DIC technology and EDA flows. 3DIC physical design and tapeout. TSV signal/power trade-offs. Chiplet placement and optimization. - EDA synthesis-place-route flow optimization for mobile product in production EDA flows. Machine.

High performance processor development- DTCO and Pathfinding for next node design in silicon foundry.- PnR aware standard cell, power grid design meeting performance, area, IR/EM requirements.- Development of approaches to improve timing and routing outcomes in processor cores.- SRAM, custom memory optimization.- 7nm/5nm/3nm silicon technology and design.

Malta, NY

7nm ADVANCED CMOS TECHNOLOGY | GlobalFoundries- Led a cross-organization engineering team (research, technology, design rules, SoC CAD flow) and worked with industry partners to create 7nm foundry CMOS technology.- Drove perf-power-area scaling to meet customer product requirements through innovations in standard cell architecture, PnR elements and SoC CAD.

14nm SOI FINFET TECHNOLOGY | IBM Semiconductor R&D- Led engineering team (integration, device, characterization) for rapid systematic yield learning in SOI finfet technology. Designed and deployed unique testchip and analytics for yield detractor detection and mitigation. 22nm SOI TECHNOLOGY DEVELOPMENT | IBM Semiconductor R&DLed design of first of a kind.

RFCMOS Design & Modeling | IBM Semiconductor R&D- Defined RFCMOS technology in 90, 65 and 45 nm nodes. Developed methods for accurate compact model extraction for RF applications. - Worked with industry and university partners to design reference circuits to demonstrate CMOS technology for mm-wave applications.Silicon-Germanium (SiGe) BiCMOS Device and.

Phd, Electrical Engineering

B.Tech, Energy Engineering (Electrical Engineering)