Bashir Mahmud Email & Phone Number

Beaverton, Or, Us

Hillsboro, Oregon, United States

Managing Analog library team consists of members in multiple geo locations focusing on Passive components. Development of Library collaterals for all active Intel nodes from the scratch with Design rule definition, architecture development and layout/parametric cell/PDK collateral development followed by Si characterization of model/design/Integration/Yield and productization.Delivered ~20 Testchips contents in the latest Intel technologies for Si data characterization from feature… Show more Managing Analog library team consists of members in multiple geo locations focusing on Passive components. Development of Library collaterals for all active Intel nodes from the scratch with Design rule definition, architecture development and layout/parametric cell/PDK collateral development followed by Si characterization of model/design/Integration/Yield and productization.Delivered ~20 Testchips contents in the latest Intel technologies for Si data characterization from feature, skew, physical layout, DRC, LVS, Extraction, floor plan, pre/post layout simulation and tape out. Foundry interface to most of Intel foundry customers including IP vendors in multiple Intel technologies. Familiarize and Train customers, Early phase DTCO and Debug and provide solution to customer issues to enable competitive Intel offering. Skills: Strategical decision making, building a strong team, Clear and crisp presentation of complex technical issues in simpler form to executive leadership. DTCO lead with internal/external customer, in depth knowledge of PDK delivery with quality, training and documentation, Pre/post layout methodology, Modeling of library components. Show less

Hillsboro, Oregon, United States

Analog Library IP Foundry Interface.Collaborated with Intel Foundry Services and technology development team to build the technical infrastructure for IFS offerings in different Intel technologiesManaged DTCO activities for Analog design.Led a group to deliver novel Analog library Offering to enable enhanced Intel Process for a competitive foundry offering.

Portland, Oregon Area

Led analog template development compatible to analog IPs of Intel Products for Intels 10nm, 7nm, 5nm and other emerging processes. Physical layout, analog IP design and Semiconductor process understanding is the key skillset needed to develop a world class analog template. As a template developer defined template fundamentals with Process and design co-optimization with optimum footprint, enhanced performance and integration flexibility for each technology. Developed templates with schematic… Show more Led analog template development compatible to analog IPs of Intel Products for Intels 10nm, 7nm, 5nm and other emerging processes. Physical layout, analog IP design and Semiconductor process understanding is the key skillset needed to develop a world class analog template. As a template developer defined template fundamentals with Process and design co-optimization with optimum footprint, enhanced performance and integration flexibility for each technology. Developed templates with schematic design, QA clean physical layout, UPF modeling, execution of tool flows for pre/post layout simulation, Reliability analysis and then QA regression for PDK delivery of the library content. Conducted training of Engineers and Mask designers throughout different organization of Intel for Template usuage details and continuously support customers with sustaining and enhancement for ease of integration. For this dynamic role need to lead multiple projects simultaneously with collaboration of many intel groups. Lead Testchip implementation, execution, testing, characterization of Silicon for template contents. Work as technical lead of Template silicon data to match targets for key template metrics through measurements, analysis, collaboration with key stake holders and by executing implementation of necessary changes. Show less

Hillsboro, Oregon

Worked as a technical lead of Intel's 14nm Back End Etest group for sustaining and enhancing challenges of 14nm process with BE parametric. In parallel, worked as Front End integration Engineer. Managed 24/7 excursion management, actively managed Process and Yield enhancement projects, owner of parametric variability improvement and led, investigated and executed with other teams the process fixes for eventual better line control. Led the BE Etest group Engineers and technicians as well led… Show more Worked as a technical lead of Intel's 14nm Back End Etest group for sustaining and enhancing challenges of 14nm process with BE parametric. In parallel, worked as Front End integration Engineer. Managed 24/7 excursion management, actively managed Process and Yield enhancement projects, owner of parametric variability improvement and led, investigated and executed with other teams the process fixes for eventual better line control. Led the BE Etest group Engineers and technicians as well led the Transistor contact process modules with directions, planning and execution for the dynamically changing 14nm process for better Yield enhancement. Show less

Hillsboro, Or

Works at development and Sustaining of Intel's innovative technologies.Worked as a Device Engineer in Intel's 45nm, 32nm, and 22nm front end process with specialization in contact segment. Expertise in Device Characterization, Process development and high volume sustaining.

Doctor Of Philosophy (Ph.D.), Solid State Electronics

Master'S Degree, Electrical And Electronics Engineering

Electrical And Electronics Engineering

Education record