Basma H. Salah , M.Sc Email and Phone Number

Develop a thorough understanding of system-level design specificationsRTL Coding/Synthesis of the digital part of Mixed Signal IPsDevelop behavioral models for the analog parts of Mixed Signal IPsDevelop advanced verification environment and test-bench componentsWorking with the mixed signal team on the co-simulation and verification of the IPsHardware verification of the digital module using cutting edge FPGA kits

Verification of 32G Ethernet PHY protocol using the following:● HDL Experience: SystemVerilog, SystemVerilog Assertions and VMM/UVM● Checker, stimuluses and VMM tests creation to test newly designed features● Monitoring regression and debugging failures, Suggesting RTL fixes.● Debugging in the environment, firmware, analog models and analog circuit.● Understanding IP and modes of operation, each feature required to be tested and plan how to be tested and regressedSupporting graduation project team through designing and verifying a 5G RTL transmitter chain.

GRD Egypt DVT Questa QA● HDL Experience: Verilog, SystemVerilog, Gate-Level Simulation (GLS) (Timing Cells and SDF), VHDL, Foreign Languages(VPI, DPI, FLI).● Regression Monitoring and debugging Failures in different Areas.● Hands-on experience with UVM, debugging regression failures which included UVM test cases and Designs.● Using different Testing methodology as Assertion-based verification using SV and VHDL assertions.● Comprehensive knowledge of Software Testing Life Cycle, Manual and Automation Testing.● Flow Automation using scripting (perl / shell / TCL / SED).● Communicating RnD and negotiating with them for the Feature specification and Quality.● Using In-House Customer Designs for new Features Functional testing and analyzing the results.● Investigating and Understanding Functional Specification, Test planning, Test cases design, execution and result analysis.

A Digital Design Engineer Internship