Bavneet Kaur Email & Phone Number

Toronto, Ontario, Canada

Toronto, Ontario, Canada

Undergoing Universal Verification Methodology training

Obtained VLSI Verification Certification from Maven Silicon.Concepts of System Verilog, Constraint random verification, Functional Coverage and UVM Concepts.

Obtained Ceritfication in Verilog HDL. Course offered verilog concepts, testbench writing and Design of various Digital blocks. Used Model Sim for Tesbench writing and Quartus Prime for RTL Design.

An initiative to upcycle waste material for making customized and personalized gifts for customers at reasonable prices.Facebook Link: https://www.facebook.com/creartcreations/Instagram Link: https://www.instagram.com/creartcreations/

Bangalore

Handled presentations, product demos, and interaction with 20 key accounts. Negotiated contracts and agreements to maximize profit.Performed lead generation, profiling, cold calling, and pre-qualification for new accounts.Created new sales opportunities within existing accounts.Organized events and conferences in prime cities to get more leads.

Bangalore Urban, Karnataka, India

Tool used: Cadence InnovusGained Hands-on experience in Block level physical implementation flow.Acquired Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure, and physical verification.

Bengaluru Area, India

Tool used: QuestasimApplied various SystemVerilog concepts like Object Oriented Programming and developed self-checking test benches using constrained random methods and inter-process synchronization techniques such as semaphores and mailboxes.Achieved 100% functional coverage for the LC3 processor project.Introduction to the Universal Verification.

Master’S Degree, Vlsi And Embedded Systems, 86.7%

M.tech

Engineer’S Degree, Electronics And Communication, 75%

Activities and Societies: Member of Editorial Group for College magazineB.tech

High School, Non Medical, 82%

schooling