Principal Fpga Design Engineer
CurrentRobotics and Digital Solutions RADFPGA design for High-tech Surgical robots, vision and robot control
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Yousef B. Bedoustani, Phd. Eng. is listed as Principal FPGA & Hardware Engineer at Johnson & Johnson MedTech, based in Santa Clara, California, United States. AeroLeads shows a work email signal at opal-rt.com and a matched LinkedIn profile for Yousef B. Bedoustani, Phd. Eng..
Yousef B. Bedoustani, Phd. Eng. previously worked as Principal FPGA Design Engineer at Johnson & Johnson Medtech and FPGA Development Leader at Teledyne Technologies Incorporated. Yousef B. Bedoustani, Phd. Eng. studied at Mcgill University.
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I did my BS in Electronics, my MS in Mechatronics, my PhD in Robotics engineering, and Postdoc at McGill University Department of Physics for cosmology instruments laboratory.Since my BS on 2003, I have experience in FPGA design, RTL design, Embedded systems, Real-Time Digital Signal Processing, Electronics hardware design for different applications.As an Electronics Engineer, I was developing FPGA and implementing Digital Signal Processing algorithms within all FPGA vendors including Xilinx, Intel (Altera), MicroChip/Microsemi, Lattice and Achronix FPGAs.Currently, at Johnson and Johnson MedTech, I am working in FPGA design of high-tech Surgical Robots. At Teledyne Technology, I was designing of FPGA, hardware, firmware and embedded software for high-speed cameras and high-speed video frame grabbers. At Morgan Stanley I was responsible for ultra-low-latency FPGA infrastructure, FPGA hardware design, FPGA firmware design and required embedded software for high frequency Trading (HFT) systems and trading algorithms.At SpaceBridge Inc. (formerly Advantech wireless), I was developing FPGA firmware for in-ground satellite communication systems. I was also implementing different complicated DSP algorithms using Xilinx, Altera, and Lattice FPGAs.At THALES Canada Avionics, I was working on flight control systems using Xilinx and Microsemi FPGAs.At OPAL-RT Technologies I was worked on Real-Time simulator and Hardware in Loop (HIL) for power electronics application. I worked on Xilinx FPGAs and NI cRIO and FlexRIO platforms via LabVIEW FPGA, LabVIEW Real-Time and NI VeriStand. As a result of my work, OPAL-RT won Product of the Year at NIWeek 2015 in Austin, TX. Moreover, OPAL-RT became the Gold Alliance Partner of NI in 2016 Program Promotion.Moreover, during my Postdoc at McGill university department of physics, I did DSP and FPGA design for ICE DAQ system that is used in South Pole (SPT) & CHIME Radio Telescopes.For my PhD, I designed and developed mechanical system and electronics control systems of a cable-driven parallel manipulator. I also implemented real-time optimization algorithm and control system using ZYNQ SoC.I am a professional VHDL, Verilog, System Verilog, Tcl, C\C++ and Python developer. I am also a professional MATLAB/Simulink, HDL coder, HDL Verifier and LabVIEW and NI VeriStand developer. I am fully familiar with board design (schematic and PCB) with Altium Designer, OrCAD, and Cadence Allegro PCB. I am also Familiar with CAD design via SolidWorks and Catia.
Listed skills include Robotics, Matlab, Simulink, Electronics, and 29 others.
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New Brunswick, New Jersey, US
Robotics and Digital Solutions RADFPGA design for High-tech Surgical robots, vision and robot control
Thousand Oaks, CA, US
FPGA and hardware design for high speed industrial camera and frame grabberLead project RDMA/RoCEV2 over 25Geth for GigE Vision Cameras
New York, NY, US
FPGA design for Ultra Low Latency trading infrastructure Ultra Low Latency Real-Time Digital Signal Processing FPGA-based High Performance Computing FPGA & SoC Embedded Software
St-Laurent, Quebec, CA
FPGA design and DSP implementation for satellite communication systems FPGA design and DSP implementation for wireless communication systems Zynq RF SOC design for wireless point to point communication linkFFT/IFFT De-Multiplexing using Intel Stratix10 and Agilex FPGARF ADC integration with Intel Agilex FPGA
Meudon, Île-de-France, FR
R&D FPGA Hardware and Firmware design for flight control systemsAvionics DO-254
Montreal, Canada, CA
FPGA design and real-time DSP implementation in FPGA for real-time simulator in power electronics and power systems applications
Montreal, Qc, CA
Postdoc at Cosmology Instrumentation Laboratory and FPGA & DSP developer for South Pole (SPT) & CHIME Radio Telescopes
Montréal, Québec, CA
Design and control of 6-DOF Cable-Driven loading simulator
Modeling, Redundancy Resolution and Control of Cable Driven Redundant Parallel Manipulator (CDRPM)
Tehran, Tehran, IR
Electronics EngineerRepair of computer hardware including motherboard, power supply, monitor, printer etc.IBM Mainframe operator
Design of communications boardsRepair of communication boards
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Yousef B. Bedoustani, Phd. Eng. works for Johnson & Johnson MedTech.
Yousef B. Bedoustani, Phd. Eng. is listed as Principal FPGA & Hardware Engineer at Johnson & Johnson MedTech.
AeroLeads has found 1 work email signal at @opal-rt.com for Yousef B. Bedoustani, Phd. Eng. at Johnson & Johnson MedTech.
Yousef B. Bedoustani, Phd. Eng. is based in Santa Clara, California, United States while working with Johnson & Johnson MedTech.
Yousef B. Bedoustani, Phd. Eng. has worked for Johnson & Johnson Medtech, Teledyne Technologies Incorporated, Morgan Stanley, Spacebridge Inc., and Thales.
You can use AeroLeads to view verified contact signals for Yousef B. Bedoustani, Phd. Eng. at Johnson & Johnson MedTech, including work email, phone, and LinkedIn data when available.
Yousef B. Bedoustani, Phd. Eng. studied at Mcgill University.
Yousef B. Bedoustani, Phd. Eng. is listed with skills including Robotics, Matlab, Simulink, Electronics, Mechatronics, Fpga, C++, and Signal Processing.
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