Seetha Vikram Shobha ‏‏‎ ‎ Email & Phone Number

Professional with 5+ years of experience in areas of Analog Layout & Memory Layout Design and Physical Verification• Proficient in designing layouts from TSMC 45nm to 3nm both in CMOS process & FinFET process.• Have good knowledge of physical verification checks like EMIR,Gridcheck,Tiecheck,Perc14.6drc,DRC,LVS,ANTENNA,ESDLUP LUP.5• Experience with cadence tools like Virtuoso schematic editor Virtuoso layout L, XL & EXL Verification tools like Calibre & Assura• Have experience of customer interactions from U.S.A & Malaysia side• Worked as Domain lead position for LNLDDR project• Worked as Domain lead position for SoundwaveDDR project• Technology nodes worked on 45nm,7nm,5nm,3nm>LNLDDR - 3nm FINFET>SoundwaveDDR - 3nm FINFET>Analog Layouts (DDR,Resistors,Capacitors) - 3nm & 45nm>FinFET process cadence virtuoso (EXL) verification tools (Assura and Calibre)>Expertise in virtuoso Layout EXL for optimized floorplanning and routing.

Listed skills include Semiconductors, Tsmc16Nm Finfet Technology, Cmos, Cadence Virtuoso Layout Editor, and 13 others.

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  Anurag Group Of Institutions

  Electronics And Communications Engineering