Benjamin Delsol Email & Phone Number

Austin, Texas, United States

UVMGen simplifies and accelerates testbench creation with built-in industry best practices, facilitating easy development, integration, and VIP reuse. Think of it as Legos for testbenches, enabling one-click integration of UVCs and environments, all implemented the right way from the beginning. Contact me or visit uvmgen.com for more information.

San Jose, California, United States

Developed 3 constrained random UVM block level testbenches for an ARM based design. Top RTL bug finder on team during the first project. Functional and code coverage closed on time and 100%.

United States

Performed L2 cache verification. Developed black box UVM predictor, modified ARM ACE UVCs, owned power management UVCs and assertions and converted testbench to uvm_reg RAL with built-in access sequences.

Austin, Texas Area

Austin, Texas

San Diego, California

• Allowed zero digital bug slips for a first generation Qualcomm sensor chip as part of a two person DV team. 18 pre-si RTL bugs found in sensor 1.0 and 26 in sensor 2.0. All Qualcomm DV milestones and reviews achieved on time.• Created test plans, developed and integrated UVM sensor agents, including drivers, monitors, scoreboard and functional coverage. Wrote constrained random test stimulus via sequences and virtual sequences to verify all sensor interfaces and transactions. RTL sensor data comparisons made against an integrated Matlab model in the scoreboard. • Employeed Qualcomm proprietary SPI-S/AHB-M VIP and provided extensive feedback to enhance VIP quality.• Scripted a uvm_reg RAL generation tool and coded uvm_reg adaptor to verify CSRs, memories and aid sequence writing.• Created a software compiler for programming sensor instruction memory. Used by analog and post-silicon sensor teams.

Folsom, California

• Introduced OVM to the Display Design team in 2010 and deployed it through integration planning, automation and training. Through this effort, the team went from zero OVM/UVM testbenches to now more than a dozen.• Developed advanced Object-Oriented Programming skills through the development of SystemVerilog testbenches, testbench infrastructure and Ruby design automation projects. Codes clean, refactors and practices Test-Driven Development.• Invented the Intel DTTC 2011 published OVM/UVM testbench generation tool called REACT. This tool is responsible for all UVM testbench scaffolding of more than a dozen testbenches in the Display team. • Coded the SystemVerilog testing infrastructure used by all of the Display teams OVM/UVM testbenches. • Traveled to Guadalajara, Mexico to provide trainings and lab exercises for a dozen new Display verification contractors. Planned and guided the startup of a new UVM Display Streamer sequence-based ULT being developed by the contractors.• Designed a test execution/progress tracking application called TestStats, which tracks test status for all Display DUTs in a MySQL database. It is the one and only resource needed by management to assess testing progress.Communication/Organization• Experienced in technical presentations to audiences of 30+ people.• Experienced as a Software and SystemVerilog mentor for the Display team.

Folsom, California

• DisplayPort design and verification experience across three Intel projects. • Rewrote the A/V mixer, cross-clock FIFO and register synchronization RTL. • Verification activities included creation of test plans and tests, running test regressions, debug of failures, implementing RTL bug fixes and ECOs. • Contributed documentation and diagrams to the DisplayPort Architectural Specification.• Created a DisplayPort OVM testbench for MultiStream verification which supported random stimulus. Developed SV coverage for tracking MultiStream mode-sets and configuration.• Created Display IO-buffer behavioral models (BMODs) for all Display related AFE ports. Maintained IO Ring connectivity to RTL/HSIO.Communication/Organization• Long term organization skills consistently enable on time milestone completion.• Experienced in constructive problem solving within groups and in one on one situations.