Benjamin Dodge Email & Phone Number

Mountain View, Ca, Us

Cupertino, California, Us

Santa Clara, Ca, Us

- Manage dynamic, global teams of 8 to 15 engineers to design and verify PC chipset components. * high speed serial packet interfaces including PCI Express Root Port, HyperTransport interfaces, and proprietary interface with partner company * units including PCIe Downstream Switch Port and Endpoint interface to pre-existing DMA devices, AMD IOMMU translation engine, and proprietary on-chip backbone interface and crossbar for PCIe switches and root complexes- Managed global team of over 30 engineers to design and verify PC chipset for the AMD workstation and enthusiast market.- Define and refine high level requirements with Architecture team and senior management.- Scope design, validation and integration timelines and resource requirements.- Coordinate with chip and other IP teams for timely and efficient integration of design components.- Drive design and validation teams in creation of micro-architecture and its implementation.

Santa Clara, Ca, Us

- Lead pre-silicon system verification team of 8-10 engineers for PC chipset with integrated GPU targeting AMD desktop market.- Drove post-silicon validation of HyperTransport interfaces and general chip bring-up including ATE for PC chipset with integrated GPU targeting AMD desktop and notebook markets.- Coordinated chip toplevel integration, DFT and pad ring for PC chipset with integrated GPU targeting AMD desktop and notebook markets.- Wrote and maintained upstream and downstream HyperTransport interface units.- Defined mirco-architecture of downstream HyperTransport interface.- Drove system random verification for PC chipset with integrated memory controller for Intel enthusiast market.- Re-wrote HyperTransport Bus Functional Model (BFM) for updated protocol revision.

10G Network Processor ASIC * Defined architecture with two senior engineers of a high-performance multi-threaded multi-processor deep-packet processor. * Implemented multi-threaded multi-issue processor core RTL including register file, execution units, load/store units, frame buffers and configurable CRC unit. Coded frame input interface and distribution block and frame output interface. Designed semaphore unit.16 port Fibre Channel and Gigabit Ethernet Storage Switch ASIC * Verified 1149.1 TAP and lead ECO equivalence checking. * Floorplanned ASIC including automated repeater insertion. Interfaced with ASIC foundry for chip physical design.

Houston, Texas, Us

VLSI Crossbar ASIC, Superdome Enterprise Unix Server * Co-wrote C++ crossbar model to prototype architecture and analyze performance trade-offs. * Coded Verilog for packet-switched VLSI crossbar ASIC. Responsible for a majority of core-logic implementation. * Designed and wrote C++ verification tool to test Verilog model. Tool tested core functionality, Control and Status Register access, and test and debug features in RTL and gatelevel models. * Responsible for project team's Synopsys synthesis methodology. Iterated through RTL changes, synthesis, placement and post-layout timing. Hand-tuned placement to meet timing goals.