Static Timing Analysis Tool: Design static timing analysis tool to analyze timing delay in synchronous IO modules of Asynchronous FPGA chip. Integrate Static timing Analysis tool to existing core software system by developing TCL interface, database interface modules and timing flow control modules. DRC checking Infrastructure: Build DRC checking modules: netlist-connectivity checking and placement checking. FPGA Infrastructure: Windows Porting: Port FPGA software from Linux to MS Windows XP(32 bits) and Vista(64 bits) Performance Improvement: Memory usage and runtime in database modules, analytical timer modules and bitstream generation modules. Enhance algorithms/data structures and build memory management modules. Tools: C/C++, TCL, Perl and Python OS: LINUX and Windows

FPGA Database Infrastructure: Performance improvement: Memory usage and run time. Develop hierarchical routing data model to support large FPGA devices. (Reduce memory to about 1/10 of device memory and about 1/2 of total CAD runtime memory for large devices.) Develop hierarchical device generation process, and generate hierarchical device files: routing data, cell data, package data, timing data, graph data, etc. FPGA Timing Function: Develop static timing engine for Synthesis based on primitive timing model and Synthesis data model. Enhance static timing engine for placer/router: Asynchronous-loop, K-longest paths, and Run-time. Support FPGA families EC/ECP/XP and DSP/DDR/PCS timing model. Reduce memory usage by automated device load/unload. Java-Based FPGA Floorplanner: Design Device and Design View. Design package-view component. Design routing congestion measure component. Data compression: Develop data compression module for foundry software system. Tools: C/C++, Java and Perl OS: Solaris, LINUX, and NTPATENTS 1. U.S. Patent Application entitled: "Hierarchical routing graph representation using super-set masters and wire-mapping tables" Inventor: Byung-Kyoo Kang and Toshikazu Endo Date: March. 12, 2008 2. U.S. Patent Application entitled: "A Grafting algorithm in FPGA device using interface template and transitive indexing" Inventor: Toshikazu Endo, Byung-Kyoo Kang, and Guanqun Zhou Date: July. 17, 2007

Conduct design and development of B-to-B e-commerce application software that provides e-commerce capability to merchandise stores.

Responsibilities include development to provide industrial strength solutions for Jasmine multimedia OODB technology.

Developed functions to provide Internet service in switching network.