Berk Akinci work email
- Valid
- Valid
- Valid
Berk Akinci personal email
Berk Akinci phone numbers
I'm an electrical design engineer and leader with extensive experience in microprocessors, network and storage devices. I design high-speed digital and mixed-signal circuits with a focus on signal integrity and reliability. I work closely with software engineers during bring-up, development and debug of drivers, operating systems and hypervisors. I work with mechanical engineers on packaging of PCB assemblies.Areas of expertise: Microprocessors (embedded, general-purpose, multi-core up to 36 cores, SoCs); High-speed circuit design; High-speed (12Gbps) serial interfaces; Logic design in Verilog; Networking devices; Layer 2 to Layer 7 networking protocols; Software/hardware integration and interaction; x86/x64 system architecture.
-
Electrical EngineerAmazonTewksbury, Ma, Us
-
Director Of Hardware EngineeringZeeveeTewksbury, Ma, Us -
Director Of Hardware EngineeringZeevee Feb 2024 - PresentLittleton, Ma, UsKey engineer and leader of the overall ZeeVee hardware engineering teamResponsible for the design, implementation, and introduction into manufacturing of ZeeVee’s advanced designs and product offerings -
Co-Founder / Chief Technology OfficerInvitrometrix Mar 2016 - PresentLowell, Ma, UsDefine the capabilities and product development goals of this newly incorporated company.Design, build and validate PCB assemblies, FPGA logic, mechanical assemblies and software. -
Vp Of R&D, Engineering / Co-FounderOnco Filtration, Inc. Jul 2022 - Feb 2024 -
Principal EngineerZeevee, Inc. Apr 2017 - Sep 2022Littleton, Ma, UsDesign advanced products in commercial and medical IP video distribution.
-
Principal Hardware Engineer / Senior Hardware EngineerCorero Network Security Dec 2012 - Mar 2017Marlborough, Ma, UsDesign, debug and validate network “First Line of Defense” devices. Devices have four 10Gbps Ethernet interfaces, a 36-core Tilera/EZchip Tile-GX microprocessor, 1600MTps DDR3 memory, 6Gbps SATA, and 5Gbps PCIe.Design, debug and validate network “Bypass” devices. Devices have four 10Gbps Ethernet interfaces, an ARM microprocessor, DDR3 memory, a 10Gbps network switch IC, and passive optical switches.Design diagnostic capabilities for in-field forensics of faults on the TileGX microprocessor using already-existing I2C/JTAG connection into the processor.Develop methods to debug and resolve infrequent hypervisor-level software faults in interrupt handling and multi-core mesh network deadlocks.Perform design verification of the new products and deliver reliable manufacturable products for sale.Develop software and scripts for manufacturing and verification testing of the new products. -
Consulting Engineer – VolunteerUniversity Of Massachusetts Lowell Jun 2014 - Jun 2016Lowell, Ma, UsCollaborate with scientists in the Biology and Biotechnology Department, and Chemistry Department.Design a high-resolution frequency counter in FPGA (0.025Hz resolution @ 10MHz input, 1Sps)Design, validate and build data acquisition (DAQ) system using low-cost FPGA and embedded µP.Design DAQ software and web-based graphical user interface and real-time visualization.Design and validate FPGA logic in Verilog: 400MSps edge sampling at SDR (designed for expansion to 800MSps DDR); FIFOs; FIFO Arbiter; SPI slave; Timers; 3 clock domains; Internal communication bus (Wishbone-based); Direct Digital Synthesizer (DDS); 4-bit 100MSps DAC.Design mechanical assembly around PCB for use as a cell-culture plate at the Biology department. -
Master'S Thesis ProjectUniversity Of Massachusetts Lowell Oct 2013 - May 2014Lowell, Ma, UsDesign and build a twelve-well QCM (quartz crystal microbalance) biosensor for cell culture application.
-
Senior Hardware EngineerOracle Corporation Feb 2010 - Nov 2012Austin, Texas, UsDesign storage subsystems for Intel-based x86 servers using 8Gpbs PCI-e Gen3, a new PCI-e form factor specification, PCI-e switch, PCI-e hot plug and 12Gbps SAS3. Provide some feedback to the PCISIG working group.Design a 34-port 6Gbps SAS2 expander board and disk backplane.Design two ARM-based embedded processor subsystems for remote management of servers.Improve design of a blade server in areas of power, 6Gbps SAS and Gigabit Ethernet.Specify design constraints and oversee the layout of the above designs.Assist software development, test development and manufacturing of the new products.Develop methods to reproduce, debug and fix highly infrequent failures that involve a mix of hardware and software.Perform design verification of the new products and deliver reliable manufacturable products for sale. -
Hardware EngineerSun Microsystems Jan 2004 - Feb 2010Palo Alto, Ca, UsDesign a SAS expander board for a 12-disk backplane supporting 3Gbps SAS and SATA disks.Design a PowerPC-based embedded processor board for remote management of servers.Design a new front end (two Gigabit and sixteen Fast Ethernet ports) for the high-performance content switch.Train manufacturing personnel to use, test and debug systems.Develop tests required to catch manufacturing defects while maintaining simple operator interface.Identify defects and component failures that interrupt manufacturing; resolve issues to resume operations. -
Hardware EngineerNauticus Networks May 2002 - Jan 2004Help move from engineering prototypes to production level Gigabit-scaled L4-L7 intelligent switches.Contribute to the inception of the next-generation products.Modify the clock generation and distribution on an 18-layer high-density board to improve signal integrity and reliability.Generate and execute tests to duplicate and debug intermittent errors. Write engineering change orders to fix errors or bring errors to the attention of responsible groups.
-
Major Qualifying ProjectWorcester Polytechnic Institute Jan 2002 - Jan 2003Worcester, Massachusetts, UsDesign and build an MRI (magnetic resonance imaging) quadrature surface coil for use in a high-field (4.7 Tesla) magnet. -
Product Development InternAnalog Devices, Inc. May 2001 - Jul 2001Wilmington, Ma, UsTest, probe and debug a Logarithmic Amplifier IC.Perform tests on a Digital Variable Gain RF Amplifier IC. -
Hardware Engineer Co-Op -- Module DesignAvaya, Inc. May 2000 - Dec 2000Morristown, New Jersey, UsModify an existing ATM module design to interface with a newer backplane.Design a test board to evaluate the performance of a Gigabit Ethernet PHY in the system.Test and debug various prototype and beta level modules.
Berk Akinci Skills
Berk Akinci Education Details
-
Worcester Polytechnic InstituteElectrical Engineering -
University Of Massachusetts LowellElectrical Engineering
Frequently Asked Questions about Berk Akinci
What company does Berk Akinci work for?
Berk Akinci works for Amazon
What is Berk Akinci's role at the current company?
Berk Akinci's current role is Electrical Engineer.
What is Berk Akinci's email address?
Berk Akinci's email address is ba****@****vee.com
What is Berk Akinci's direct phone number?
Berk Akinci's direct phone number is +197893*****
What schools did Berk Akinci attend?
Berk Akinci attended Worcester Polytechnic Institute, University Of Massachusetts Lowell.
What skills is Berk Akinci known for?
Berk Akinci has skills like Network Security, Science.
Who are Berk Akinci's colleagues?
Berk Akinci's colleagues are Lucas Marques, Naveen Dsouza, Gabriel Sosa, Jason Camacho, Egor Pyanov, Rashid Khan, Ryan Clendenin.
Free Chrome Extension
Find emails, phones & company data instantly
Aero Online
Your AI prospecting assistant
Select data to include:
0 records × $0.02 per record
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial