Beth Keser, Ph.D. Email and Phone Number
Beth Keser, Ph.D. work email
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Beth Keser, Ph.D. personal email
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BETH KESER, Ph.D. is a recognized global leader in the semiconductor packaging industry with over 25 years of experience. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 49 US patents and patents pending and over 50 publications in the semiconductor industry.For over 7 years, Beth led the Fan-Out and Fan-In Wafer Level Packaging Technology Development and NPI Group at Qualcomm where she and her team qualified over 50 products resulting in over 10 billion units shipped--technology consumers around the world enjoy in mobile phones. Following that, Beth led Intel's worldwide Packaging & Systems Technology department for 7 years. Beth is currently VP of Manufacturing Technology at Zero ASIC.Beth is also an IEEE Fellow and IEEE EPS Distinguished Lecturer who chaired IEEE EPS’s 2015 ECTC. Based in San Diego, Beth was the President of the International Microelectronics Assembly and Packaging Society (IMAPS) from 2021-2023 and is currently Past President. Beth has published two edited volumes: "Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Applications Spaces" (Wiley, 2021) and "Advances in Embedded and Fan-Out Wafer Level Packaging Technologies" (Wiley, 2019). In 2021, Beth received the IEEE EPS Exceptional Technical Achievement Award for contributions in the field of Fan-Out Wafer Level Packaging. Finally, Beth has lectured at Cornell University, Georgia Tech, UCLA, Purdue, Hong Kong University of Science and Technology, Florida International University, Portland State University, and the Department of Commerce's Bureau of Industry and Security (BIS) and given keynotes and participated in panels at prominent electronic packaging and semiconductor conferences worldwide. Currently, Beth teaches professional development courses at IMAPS conferences and online at IMAPS Academy (imaps.org).
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Vp Of PackagingVolantis SemiconductorSan Diego, Ca, Us
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Vp Of Manufacturing TechnologyZero Asic Aug 2023 - PresentCambridge, Massachusetts, Us -
Senior Principal Engineer & Manager, Package EngineeringIntel Corporation Dec 2016 - Aug 2023Santa Clara, California, Us -
Principal Engineer/Manager; Package EngineeringQualcomm Jul 2009 - Dec 2016San Diego, Ca, UsManage cross-functional team to develop and deploy electronic packages for Qualcomm products.Engage with multiple assembly suppliers to qualify their technology and standardize design rules, package structure, materials, and processes across suppliers where needed. Visit suppliers worldwide to ensure compliance to qualification plan and audit assembly lines.Engage with materials and tool suppliers in supply chain to assess offerings and ensure best capability being used for Qualcomm technology development and products.Responsible for the low cost package technology roadmap including the development of latest materials, structures, solder ball alloys, and design rules. -
Package Development R&D ManagerFreescale Semiconductor (Formerly Motorola Semiconductor Products Sector) Mar 2003 - Jul 2009Austin, Texas, UsLead packaging development team that developed a reliable, manufacturable, low-cost FOWLP technology for consumer, industrial, and automotive applications.Directed a team of R&D engineers and technicians in Tempe and Austin. Installed a $35M 300 mm pilot line to demonstrate the new technology in large scale and hired manufacturing staff to characterize and qualify the line.Benchmarked competing technologies and developed strategies to provide best in class packaging solutions. Completed IP landscaping regularly and led team to meet annual patent filing goals. -
Product Packaging Engineering ManagerMotorola Semiconductor 2001 - 2003Austin, Texas, UsLead team of engineers responsible for assembly of all new product introductions for Phoenix wireless and automotive business units.Qualified packages at new subcontractor assembly sites and new packages such as WB-CSP, FCCSP, QFN, HQFP, FP SOIC, RF Modules, and BCC. Reduced package cost by qualifying new materials or completing factory consolidations.Resolved issues in the factory at saw, die bond, wirebond, mold, plating and singulation.
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Project Manager Of Wlp Technology DevelopmentMotorola Semiconductor Dec 1997 - 2001Austin, Texas, UsLead a project team of over 20 people to fabricate, assemble, test and characterize reliability of WLP.Implemented a peripheral to area array bondpad redistribution process.Established recipes for coating and imaging of BCB and polyimide photoimageable dielectrics.
Beth Keser, Ph.D. Skills
Beth Keser, Ph.D. Education Details
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Cornell UniversityMaterials Science And Engineering -
University Of Illinois Urbana-ChampaignMaterials Science And Engineering
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Webster High School
Frequently Asked Questions about Beth Keser, Ph.D.
What company does Beth Keser, Ph.D. work for?
Beth Keser, Ph.D. works for Volantis Semiconductor
What is Beth Keser, Ph.D.'s role at the current company?
Beth Keser, Ph.D.'s current role is VP of Packaging.
What is Beth Keser, Ph.D.'s email address?
Beth Keser, Ph.D.'s email address is be****@****tel.com
What schools did Beth Keser, Ph.D. attend?
Beth Keser, Ph.D. attended Cornell University, University Of Illinois Urbana-Champaign, Webster High School.
What skills is Beth Keser, Ph.D. known for?
Beth Keser, Ph.D. has skills like Semiconductors, R&d, Design Of Experiments, Packaging, Engineering Management, Ic, Failure Analysis, Semiconductor Industry, Cross Functional Team Leadership, Silicon, Engineering, Analog.
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