Beth Richard Email & Phone Number

Cambridge, England, United Kingdom

Menlo Park, Ca, Us

* Sr. Silicon IP Execution Engineering Manager within Facebook Agile Silicon Team from Jan-2020 to present. Managed team responsible for delivery of all execution aspects of a complex IP block (Design, Verification, and Physical Design) to the SoC teams.* Silicon Design Engineering Manager within Facebook Agile Silicon Team from Sep-2018 to Jan-2020.Design team manager responsible for delivery of µArchitecture and Design for IP blocks for AR/VR research and products within the Facebook Agile Silicon Team.* Senior Silicon Design Engineer within Oculus VR from Aug-2017 to Sep-2018.µArchitect and Design lead for IP blocks within the Oculus Product, Oculus Research, and Facebook Reality Labs teams.

developed a consumer oriented Augmented Reality system that broadcasts holographic images onto retro-reflective material through glasses mounted projectors and uses camera systems to determine orientation of the head and positions of objects that interact with the projected scenes.• Responsible for the camera image processing FPGAs. Developed logic modules and integrated other engineer’s modules. Supported Firmware and PCB engineers throughout development and bring-up of several generations of prototypes. Experience with Lattice and Xilinx FPGAs, IP modules, and tools; Developed QuadSPI, I2C, AXI-4 Bus master and targets, image processing functions, Integrated MIPI IP.• Wrote specifications for interfaces between the FPGAs and the MCU firmware and system software.• Wrote LUA, JavaScript, HTML, and C programs to display and interpret received data and images in shell based and browser based tools for debugging and as reference models for the software team.

Santa Clara, California, Us

Visual and Parallel Computing Group - Architecture Team.Execution Unit (GPGPU processor) architect. Focus on correlating performance model to actual hardware performance and on Instruction Set optimizations. Performance model written in C++ and System C, with Instruction Set optimization analysis in Perl.Chipset and SoC Group, Platform Controller Hub Team.USB Microarchitect for the Platform Controller Hub focusing on USB2 and USB3 Port and Link Layer. Emphasis on extreme performance while aggressively reducing power footprint by clock and power well gating.

Dallas, Tx, Us

Digital and Mixed-Signal ASIC Design of PCI Express stand-alone PHY, Bridges, Switches and Endpoint devices as well as SATA interfaces in a USB 3.0-SATA bridge device.Digital modeling and testbench generation of Mixed-Signal ASIC circuits.

Houston, Texas, Us

Designed Chipset ASICS for High Performace Servers. * PCI Hot Plug proof-of-concept controller which drove the Industry Standard and later became a product.* Several sequential projects designing the Memory and I/O Chipsets for 4, 8, 16, and 32 processor Proliant servers. Created high-availability memory solutions including hot-plug RAID RAM where memory could be replaced, upgraded, or added without shutting down the system, with only a 25% overhead in memory (compared to the competitor's 100% overhead).Designed Memory queueing and ordering rules tracking modules, participated in synthesis and full-scan test insertion.

Houston, Texas, Us

Compaq was purchased by HP in 2002. See HP entry for details.

Us

Designed Systems ASICs for Amiga Computers.* Grace-Control and address side of Processor to Chipset Bridge for the Cost-Reduced Amiga CDTV (CDTV-CR).* Motivator-Bus interface, memory control, and DAC driver for a Scan Converting Memory Buffer system allowing Amigas to deliver HUGE resolutions.* MPEG 3000-Proof-of-concept MPEG Decoder board for use in the Zorro-II bus found in Amiga 3000s and Amiga 4000s. Based on C-Cube Video Decoder and LSI Logic Audio Decoder. Reference design for Amiga CD32 Full Motion Video (FMV) cartridge.* Akiko-Integrated Custom CD drive interface, Chipset Bridge, 8520 Interface Adapters, IDE Interface, and Chunky-to-Planar Graphics Format Converter used in Amiga CD32.* CD1200-Plug in card for Amiga 1200 that included the Akiko chip, and an FPGA to control Akiko, control a Memory SIMM, and processor expansion socket for a Motorola 68030. An external CD unit based on the Amiga CD32 was connected via a cable with expansion capabilities for FMV.

Boston, Ma, Us

Utica : 1986-1989 - AN/APG-67 team member. Design of "pulse compressor", "channel balance" (digital AGC statistics), and "test Interfaces" boards in a Digital Signal Processing (DSP) system of a small airborne radar. Also design of a spread-spectrum receiver for digital communications over the radar beam.Syracuse: 1989-1991 - AN/BSY-2 team member. Flex-Net (network system) link layer board architecture team and ASIC designer. Designed datapath ASIC with interfaces to processor busses, high speed serial busses, and FIFO memories.

Bsee, Electrical Engineering

Physics

Education record