Brian Grant Email & Phone Number

Menlo Park, Ca, Us

With Alexis Richardson and Jesper Joergensen, developing a new paradigm for provisioning, deploying, and operating cloud applications and infrastructure.

Mountain View, Ca, Us

Google Cloud Application Ecosystem and Developer Experience (Uber Tech Lead, 2023-2024)Steered Google Cloud API standards (aip.dev) and Infrastructure as Code efforts. Guided SDK, CLI, and console autogeneration and evolution.Configuration & Policy Automation (Uber Tech Lead, 2020-2022):Lead declarative configuration projects:https://kpt.dev/guides/rationalehttps://github.com/kubernetes-sigs/kustomize/https://cloud.google.com/anthos/config-managementhttps://cloud.google.com/config-connector/docs/overviewKubernetes (original architect and API design lead of Kubernetes, 2013-2019)Defined the project's scope, architecture, and API model, and shaped the system design based on my experience from Omega and Borg. Declarative configuration innovator: creator of "apply", kustomize, kpt, and porch. Coined "Kubernetes Resource Model" and "Configuration as Data". Founding member of the Kubernetes Steering Committee. Founder of Kubernetes SIG Architecture. Inaugural member of the CNCF Technical Oversight Committee. Wrote the definition of "Cloud Native".Background of the Kubernetes project is described here:https://medium.com/@bgrant0607/the-technical-history-of-kubernetes-2fe1988b522ahttps://medium.com/@bgrant0607/kubernetes-the-road-to-1-0-525a9420fdf0https://www.youtube.com/watch?v=ftKZN6k-K1khttp://queue.acm.org/detail.cfm?id=2898444https://kubernetespodcast.com/episode/043-borg-omega-kubernetes-beyond/Omega (founder, tech lead 2011-2012): http://research.google.com/pubs/pub41684.htmlBorg (tech lead, 2009-2010): http://www.wired.com/2013/03/google-borg-twitter-mesos/all/ http://research.google.com/pubs/pub43438.htmlMulti-core initiative (tech lead manager and intergrouplet founder, 2007-2008):Initiated several efforts to expand use of multi-threading in Google's C++ codebase: Linux NPTL benchmarking, new C++ synchronization primitives, g++ compiler thread-safety annotations, thread profiling, multi-threaded HTTP server, education and documentation

Lead software engineer/designer, and employee #6 at a small software startup developing a software platform for high-performance computing on commodity GPUs and multi-core x86 processors -- yes, HPC on GPUs in 2005-2007 -- a bit too early. Played key roles in many areas, including product definition and design, software development (in C++), test-plan development, product roadmap development, advanced development, process development, patent filings, presentations, pitches, ... For example, designed a dynamic SPMD kernel generator for fused array-level operations and HLSL compiler. Debugged subtle GPU architectural bugs and performance issues. Also made major contributions to the design of the system's runtime and the profiler. Lead overall design of the multi-core product using SSE and multi-threading. Directly managed up to 5 other engineers and successfully guided several projects to completion.

Advised company regarding contract negotiations with 3rd party to develop compiler toolchain for embedded multi-core DSP chip. Helped plan software toolchain roadmap and compiler tool development schedule. Helped write specifications for tools and their input languages.

Us

Technical lead and senior software developer, with a focus on performance. Built an aggressive VLIW compiler backend and profile-guided whole-program link-time optimizer for Transmeta's Efficeon architecture: interprocedural register allocation and scheduling, forwards and backwards dataflow optimizations, ISA-specific optimizations, DWARF debug info remapping, ... Implemented and enhanced optimizations in dynamic binary translator (Code Morphing Software) and VLIW compiler backend. Developed online policies controlling multiple "gears" of translation, adaptive retranslation, and dynamic frequency/voltage scaling. Isolated, characterized, and/or worked around several major frequency-limiting paths in the 90nm generation Efficeon. Implemented and supervised much of the software-tools work for the 3rd-generation Efficeon core, which included new and changed instructions and major new architectural features.

Livermore, Ca, Us

Over 3 summers, investigated PVM and MPI message-passing performance, implemented collective-communication algorithms for massively parallel distributed-memory multi-computers, ported a global climate model to MPI, and analyzed message-passing performance of the climate model using ParaGraph and Pablo.

Armonk, New York, Ny, Us

Fun fact: I worked closely with https://en.wikipedia.org/wiki/Marc_Ewing.

Ph.D., Computer Science

Bs, Computer Science, Mathematics