Bradley Grove Email & Phone Number

Amherst, New York, US

• Supervises a team of five engineers developing device drivers and user mode configuration utilities for ATTO’s storage and network devices.
• Leading development of new user focused tool used to optimize high speed Ethernet performance.
• Works with other ATTO engineering teams to improve engineering processes. Member of task force that developed internal standards for employee development, performance evaluations, and source control management.
• Designed continuous integration pipeline for ATTO’s driver products using Jenkins and Robot Framework
• Developed Ethernet TX path and user mode interface for FibreChannel and SAS OpenSolaris device drivers

Amherst, New York, US

• Developed and obtained VMware certification for ESXi drivers for ATTO's FibreChanel and SAS HBA devices.
• Created open source esas2r driver for ATTO's 6G RAID HBA and submitted for inclusion in Linux mainline kernel. Contributed pm80xx driver patched to Linux kernel to allow compatibility with ATTO 6G and 12G SAS HBAs.
• Maintained ATTO’s closed source Linux drivers for FibreChannel, SAS and NIC devices.

• Part of engineering team developing Altera's Platform Designer product, a tool for creating interconnect logic to connect intellectual property (IP) functions.
• Created a language for component platform definition, allowing both internal and external IP developers to add their IP components to Platform Designer.
• Engineering team utilized Scrum with continuous integration and heavy emphasis on test driven development.

• Responsible for intellectual property core infrastructure development team, creating software tools and processes to aid in the development of over forty Altera MegaCore products as well as partner developed IP.
• Supervised five software engineers. Planned staffing of projects, maintained project schedules.
• Responsible for engineering for Altera's megafunction partner program (AMPP). Provided technical support to third party developers seeking to integrate their IP with Altera's design tools.

• Designed and developed PCI Compiler, a tool for customizing Altera's PCI IP product, and created device driver for Altera's PCI development kit demo board.
• Worked with Altera's OEM partners, including Mentor Graphics and Synopsys, to allow use of Altera IP in third party EDA tools.

• Project leader for Speedwave VHDL simulation product. Identified analysis and simulation performance bottlenecks.
• Designed and implemented a compressed library format for the Speedwave VHDL analyzer, decreasing the size of library files by 75%.
• Responsible for LMSI hardware modeler and LMG SmartModels interfaces.
• Owned synthesis engineering relationships with Lucent and Actel. Gathered data, interpreted results and suggested improvements in vendor specific optimizations resulting in improvements in speed and area performance.
• Project lead for Silcsyn VHDL language input engine. Integrated ViewFSM state machine optimization engine into Silcsyn synthesis tool.

North Reading, MA, US

• Designed and implemented VHDL readers and writers for LASAR simulation product using C.
• Designed VHDL simulation front end for LASAR behavioral simulation tool.

Bachelor Of Science (Bs), Computer Science

Bachelor Of Science - Bs, Computer Science