Bharath Kumar Changala Email & Phone Number

Hello LinkedIn community! 👋>>I am a recent graduate with a passion for physical design in the semiconductor industry. My academic journey has equipped me with a strong foundation in VLSI principles and ASIC design, and I am excited to apply these skills in a real-world setting.>>Completed Physical Design Course from May 2023 to Oct 2023 from Takshila Institute of VLSI Technologies.>>During this 6month internship i gained good knowledge on CMOS basics, Digital Electronics ,Verilog basics ,Linux and Tcl Scripting ,Synthesis and Static Timing Analysis ,PNR and Signoff checks.>>Solid understanding of block level Physical Design and verification concepts like [ Floorplan, Powerplanning, Placement, Cts , Routing , timing closure, power optimization ].>>Proficient in Synopsys IC Compilers and PrimeTIme for ASIC design and physical implementation.>>Eagerness to learn and adapt to new technologies and methodologies

• 

  Physical Design Trainee

  Takshila Institute Of Vlsi Technologies

  May 2023 - Present - Marathahalli

  Project Title: ORCA_TOPDuration: May'23 -Oct'23I had the privilege of working on an intensive project during my time at Takshila VLSI Institute, focusing on pnr and Timing closure. This hands-on experience allowed me to apply theoretical knowledge gained in the classroom to real-world challenges in the field of physical design.Key Responsibilities:^ Chip Design and Layout: Led the design and layout of specific blocks ensuring adherence to industry standards and best practices.^ Timing Closure: Implemented strategies for timing closure, optimizing clock networks, and resolving timing violations to enhance overall chip performance.^ Power Optimization: Executed power optimization techniques, contributing to the development of energy-efficient designs.^ Tool Proficiency: Developed proficiency in Synopsys ICC ,Primetime employing them for tasks such as PNR and Timing Closure.##This project was a significant learning experience, allowing me to deepen my understanding of timing closure, power optimization. I honed my ability to work effectively in a team, communicate technical concepts, and adapt to the dynamic nature of semiconductor projects.##The experience gained from this project has solidified my passion for physical design in VLSI. I am eager to apply these skills and insights in my professional journey, contributing to the advancement of semiconductor technology.