Core Expertise: With a robust background in ASIC/FPGA Architecture Design, RTL Coding, Simulation, and adeptness in Low Power Methodologies, Lint CDC & RDC analysis, Synthesis, Static Timing Analysis, Formal Verification, and Documentation, I am at the forefront of technological innovation and precision engineering.Knowledge of ASIC Products: My expertise is showcased through my contributions to Nvidia's premier GPU and CPU product lines, focusing on the design and verification of cutting-edge low-power features. Further, my work on Synopsys' USB 3.2/4 IP design and verification has honed my skills in Link and protocol adapter layers, enriched by exposure to the xHCI specification, and AXI and AHB protocols.AI Expertise: Proficient in AI/ML, I specialize in automating ASIC Front-End tasks, developing AI models that revolutionize design and verification processes. This includes Specification parsing, generating test lists tailored to design changes, and enhancing bug triaging and debug assistance.Tool Exposure: I possess hands-on experience with EDA tools including Spyglass/VC Spyglass, VC Formal (FPV, SEQ, AEP & FLP app modes), Design Compiler, Fusion Compiler, Timing Constraints Manager (previously FishTail), VCLP, Verdi, and CoreTools. Additionally, I am proficient in project support tools like Perforce, Git, Jira, and Confluence.Language Proficiency: My technical repertoire includes advanced skills in Verilog & System Verilog, Python, Perl, Tcl, and Shell scripting, enabling me to tackle complex engineering challenges with innovative solutions.My LinkedIn profile serves as a testament to a career dedicated to pushing the boundaries of ASIC/FPGA design and AI's transformative potential in engineering.