Bhargav S
AeroLeads people directory · profile

Bhargav S Email & Phone Number

Senior ASIC Design Engineer at Qualcomm
Location: Bengaluru, Karnataka, India 6 work roles 4 schools
LinkedIn matched
✓ Verified Jul 2026 3 data sources Profile completeness 86%

Contact Signals

LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
Role
Senior ASIC Design Engineer
Location
Bengaluru, Karnataka, India
Company size

Who is Bhargav S? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Bhargav S is listed as Senior ASIC Design Engineer at Qualcomm, a with 48952 employees, based in Bengaluru, Karnataka, India. AeroLeads shows a matched LinkedIn profile for Bhargav S.

Bhargav S previously worked as ASIC Design Engineer II at Nvidia and ASIC Design Engineer I at Synopsys Inc. Bhargav S holds Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering, 9.6 from B. M. S. College Of Engineering.

Company email context

Email format at Qualcomm

This section adds company-level context without repeating Bhargav S's masked contact details.

Qualcomm

Review company-level records connected to Bhargav S before choosing the right outreach path.

Profile bio

About Bhargav S

Core Expertise: With a robust background in ASIC/FPGA Architecture Design, RTL Coding, Simulation, and adeptness in Low Power Methodologies, Lint CDC & RDC analysis, Synthesis, Static Timing Analysis, Formal Verification, and Documentation, I am at the forefront of technological innovation and precision engineering.Knowledge of ASIC Products: My expertise is showcased through my contributions to Nvidia's premier GPU and CPU product lines, focusing on the design and verification of cutting-edge low-power features. Further, my work on Synopsys' USB 3.2/4 IP design and verification has honed my skills in Link and protocol adapter layers, enriched by exposure to the xHCI specification, and AXI and AHB protocols.AI Expertise: Proficient in AI/ML, I specialize in automating ASIC Front-End tasks, developing AI models that revolutionize design and verification processes. This includes Specification parsing, generating test lists tailored to design changes, and enhancing bug triaging and debug assistance.Tool Exposure: I possess hands-on experience with EDA tools including Spyglass/VC Spyglass, VC Formal (FPV, SEQ, AEP & FLP app modes), Design Compiler, Fusion Compiler, Timing Constraints Manager (previously FishTail), VCLP, Verdi, and CoreTools. Additionally, I am proficient in project support tools like Perforce, Git, Jira, and Confluence.Language Proficiency: My technical repertoire includes advanced skills in Verilog & System Verilog, Python, Perl, Tcl, and Shell scripting, enabling me to tackle complex engineering challenges with innovative solutions.My LinkedIn profile serves as a testament to a career dedicated to pushing the boundaries of ASIC/FPGA design and AI's transformative potential in engineering.

Current workplace

Bhargav S's current company

Company context helps verify the profile and gives searchers a useful next step.

Qualcomm
Qualcomm
Senior ASIC Design Engineer
Bengaluru, KA, IN
Website
Employees
48952
AeroLeads page
6 roles

Bhargav S work experience

A career timeline built from the work history available for this profile.

Senior Asic Design Engineer

Bengaluru, Ka, In

Asic Design Engineer Ii

Bengaluru, Karnataka, India

As as an ASIC Engineer in the Central Low Power Team of Nvidia,1. I work on designing low-power features for the most advanced GPU and CPU products.2. I work on leveraging Formal Verification for Power-aware verification.

Asic Design Engineer I

Bengaluru, Karnataka, India

As a part of the USB Design team, I was responsible for the following:1. Design Ownership: I work on the Link and Protocol Adapter modules of the controller where I work on incremental design enhancements, simulation debug, assertion modelling and doc updates.2. Tool Exposure: I have extensively worked on Spyglass and VC Spyglass tools for Lint, CDC and RDC enhancements. I maintain the controller's compliance with system-level RAL, synthesis tool flows, and Synopsys TCM tool. I… Show more As a part of the USB Design team, I was responsible for the following:1. Design Ownership: I work on the Link and Protocol Adapter modules of the controller where I work on incremental design enhancements, simulation debug, assertion modelling and doc updates.2. Tool Exposure: I have extensively worked on Spyglass and VC Spyglass tools for Lint, CDC and RDC enhancements. I maintain the controller's compliance with system-level RAL, synthesis tool flows, and Synopsys TCM tool. I have also been exposed to Synthesis tools like Design Compiler, Fusion Compiler and Power analysis tools like VCLP.Apart from the technical exposure, I have also been trained on Soft Skills and am also an active volunteer in Nex-GEN ERG and CSR groups of Synopsys Show less

Jul 2022 - Jan 2024

Technical Intern

Bengaluru, Karnataka, India

As a part of the USB Design Team, I have learnt about CDC, RDC, and USB Specification and have also contributed to the development and enhancement of the USB 3.2 Controller. I have worked on Spyglass, VC Spyglass, and VC Formal Tools for Lint and CDC goals.

Feb 2022 - Jul 2022

Software Engineer Intern

Bengaluru, Karnataka, India

I worked on an IOT based project under the Connected Buildings branch of Honeywell Organisation. I automated the Smoke Testing of Samba Application using Selenium.

Apr 2021 - Jun 2021

Business Automation Intern

Bengaluru, Karnataka, India

I worked on developing an autonomous software for parsing textual documents in any format (readable or non-readable) to extract necessary data fields. It is built using a python backend and JavaScript based User-Interface. It can handle various kinds of document structures and has been rigorously tested.The use cases include tax invoice parsing, bank document parsing and other company document parsing for automatic data entry.

Jul 2020 - Apr 2021
Team & coworkers

Colleagues at Qualcomm

Other employees you can reach at qualcomm.com. View company contacts for 48952 employees →

4 education records

Bhargav S education

Puc, Pcme, 97.33%

Base Education

Activities and Societies: Pure science stream training and applied lab exposure Was a part of the toppers batch run at the Base.

Sslc, State Syllabus, 98.88%

Hymamshu Jyothi Kala Peetha

Activities and Societies: IT quizes, Science Fairs, Badminton, Volley Ball, Table tennis Was enithusiastic about science and maths.

FAQ

Frequently asked questions about Bhargav S

Quick answers generated from the profile data available on this page.

What company does Bhargav S work for?

Bhargav S works for Qualcomm.

What is Bhargav S's role at Qualcomm?

Bhargav S is listed as Senior ASIC Design Engineer at Qualcomm.

Where is Bhargav S based?

Bhargav S is based in Bengaluru, Karnataka, India while working with Qualcomm.

What companies has Bhargav S worked for?

Bhargav S has worked for Qualcomm, Nvidia, Synopsys Inc, Honeywell Technology Solutions Lab Private Limited, and Sarci.In.

Who are Bhargav S's colleagues at Qualcomm?

Bhargav S's colleagues at Qualcomm include Rajender Kandimalla, 李傳源Tony Lee, Praveen Kumar Katoj, Rahul Pandey, and James Zhou.

How can I contact Bhargav S?

You can use AeroLeads to view verified contact signals for Bhargav S at Qualcomm, including work email, phone, and LinkedIn data when available.

What schools did Bhargav S attend?

Bhargav S holds Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering, 9.6 from B. M. S. College Of Engineering.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.

People with similar names

Check these profiles if this is not the Bhargav S you were looking for.

View similar profiles