Managing multiple products for prime Qorvo customer from design phase to full manufacturing by coordinating with customer, design, test, planning and supplier teams. Developing ATE test coverage and specifications along with yield monitoring and removing yield detractors as products ramp to full scale production generating $100M+ revenue till date.Serve as key technical lead for both, internal and external customers regarding supplier fab events impacting quality and performance on Qorvo products. With strong knowledge of IC wafer fabrication process and knowledge of Qorvo products functionality validated multiple CIP and PCNs requests from multiple suppliers.Interface with overseas test and assembly teams for on-time qualifications and ramp for high volume manufacturing in product development cycle. Provide on-going monitor and support for resolving yield detractors while product is full production to reduce scrap cost and save on test time.Collaborate with external wafer suppliers and test vendors, quality, characterization and planning for data driven approach for disposition of risky wafers and to meet customer demands. Helped make data-driven decisions that has saved millions to the company by avoiding unnecessary re-call of the Qorvo parts.Lead the project to share the die sort test data with our multiple silicon suppliers and co-ordinate with them on a weekly basis for continuous improvement of yield and performance on Qorvo products.

Perform yield, parametric and process window analysis on DOE/SRAM structures and give feedback to relevant process integrators and module owners about yield detractors, root cause for fail modes and address top issues with the process in the grand pareto.Developed automation system for data analysis and report generation in R. Used to monitor data on individual lots and for weekly and monthly trends on electrical and optical signals, providing other engineers with easy access to setup calculations and to perform data analysis. Worked on regular bases to with the device, integration and module teams to bring a complete view on yield and performance of different splits introduced in the process.Development of DOE test structures embedded in layout. Test site owner for the eKerf (scribe) content for 7nm development.Relevant tools: Data Analysis, R, RShiny, Characterization, Cadence SKILL and Layout, testsite design.

Developed measurement techniques for the high speed real time measurements and analysis of human breath.Developed a novel analytical technique for improving the selectivity of highly sensitive plasmonic gas sensor.Extensive analysis of the data to determine the different transient and transport behavior of the sensor and to determine the relevant polymer-gas analyte combination for the sensor.Hardware Trojan detection in Integrated Circuits George Washington UniversityDeveloped a novel technique for detection of different hardware trojan in integrated circuits.Demonstrated hardware trojan detection down to level of single transistor.Developed the experimental hardware setup for the detection of hardware trojan in integrated circuits.Proposed a complete methodology (hardware and software combined) to detect hardware trojans in integrated circuits.Relevant tools: Cadence, Lumerical FDTD, Lumerical Device, MATLAB, Labview.

My research work involves, design, fabrication, characterization and testing of plasmonic sensors for chemical gas sensing. Plasmonic structures can be used for many different applications like chemical and biological sensing, building optical circuit elements etc. I performed FDTD analysis on different structures using Lumerical's FDTD tool. My research also involved use of CVD graphene. We were able to develop a novel recipe for CVD graphene transfer. CVD graphene transfer was demonstrated on transfer to Silicon substrate.The plasmonic sensors were tested for different analytes and can be used for detection of different chemical warfare agents in department of homeland security and also for pollution monitoring and for many different applications. The sensitivity of these sensors can be tuned from a few ppm to a few tens of ppb range.I also developed an introductory course on nanoelectronics for seniors and graduate students. I was the teaching assistant for this course for three years (Fall 2011 - 2013).

I was working with the custom ASIC Group. I was mainly involved in the design of the prescalar and the PFD and had to deal with the phase noise analysis. I worked on the IBM's 6wl and the ATMEL technology.

I taught courses on Signal Processing, Introductory courses on basic electronics, Hardware Instrumentation, Communication engineering to undergraduate students.