Results-driven Physical Design Engineer with hands-on experience in ASIC design, specializing in Place and Route (PnR), floorplanning, and timing closure. Proven expertise in managing end-to-end physical design flow from block-level floorplanning to tape-out and good knowledge on SoC level physical design. Skilled in physical verification, signal integrity, power integrity, and the development of methodology flows to optimize design efficiency. Adept at utilizing scripting languages to analyze reports, drive rapid timing closure, and address technical issues in collaboration with cross-functional teams and customers. Eager to leverage my technical expertise and problem-solving capabilities to address design challenges and deliver high-quality solutions.1. PnR (Place and Route) – Core responsibility for the ASIC design flow.2. Floorplanning – Critical for the arrangement and layout of design blocks.3. Physical Verification – Ensuring design accuracy and adherence to physical constraints.4. Timing Closure – Closing timing gaps to meet performance targets.5. Signal Integrity – Managing and ensuring signal strength and stability.6. Power Integrity – Minimizing noise and ensuring reliable power distribution.7. Scripting – Using scripting languages (TCL, Python, Perl) to automate processes and optimize timing.8. Methodology Development – Developing and maintaining design flows for PnR.9. Technical Communication – Engaging with customers and teams on technical issues and design requirements.10. Tape-out – Finalizing the design and preparing it for manufacturing.