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@intel.com
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2 phones found area 319
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Billy Mills is listed as Verification Engineer at Intel Corporation, a with 10 employees, based in Hillsboro, Oregon, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 319, and a matched LinkedIn profile for Billy Mills.
Billy Mills previously worked as Verification Engineer at Rockwell Collins and Verification Engineer at Verif Pros. Billy Mills holds Bsee, Electrical Engineering from The University Of New Mexico.
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AeroLeads found 1 current-domain work email signal for Billy Mills. Compare company email patterns before reaching out.
A Career that includes 35 ASIC/SOC's design and/or verification, 3 Virtex7 FPGAs, 3 high speed circuit packs, 6 Standard Cell Libraries, and two DWDM telecom boxes. Currently specializing in ASIC/FPGA/SOC Verification using UVM. SOC/ASIC/FPGA Verification and Program ManagementUVM, OVM, System Verilog, Assertions, Functional Verification, and Specman. Projects including Multi-ARM and Multi-Atom ASICs, PCIE3.0 VIP, Xilinx VIP, Memory Controllers VIP, and 10G Ethernet cores. Expertise in PCIE 3.0, DDR, ARM, AMBA including AXI4, Denali VIP, 10GE and G.709. SOC/ASIC/FPGA Design and Program ManagementVerilog RTL, Assertions, Synopsys Design Constraints and Primetime STA. Configurable ARM/AMBA and Memory Controller IP. Four SOC/Buss platform patents. Projects including Multi-ARM ASIC's with multiple Ethernet cores. Design using Xilinx Virtex-7 FPGAs using ISE and Xilinx IP including Zync-7000.Telecom DWDM Systems EngineeringExperience with G.709, SONET, Next Gen SONET, and 10GE/40GE/100GE Ethernet. SFP/XFP/SFP+ optics modules.DWDM System/Board Design EngineerDeveloped 3 high speed Circuit Packs using Orcad, Viewdraw, and PADS. Used Microstrip and Rogers to route high speed 100 ohm differential traces at >10Gbps. Specialties: SystemVerilog, UVM, OVM, ARM, Atom, AMBA, AXI, PCIe 3.0, DDR,. Python, Perl, C++, Microsoft Project, Design Complier, Modelsim, VCS, Silos, Primetime, CVS, Spice, Agile, Viewdraw, Orcad, G.709, SONET, 10G Ethernet
Listed skills include Asic, Verilog, Systemverilog, Soc, and 23 others.
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A career timeline built from the work history available for this profile.
Santa Clara, California, Us
Developed REUT OVM test bench and tests (12,246 lines of code). Worked with Intel PCIE BFM to develop P0 and G0 tests and test bench modules. Lead PCIE BFM issues and bug meetings and follow up. Used Intel development tools and flow.
Cedar Rapids, Iowa, Us
Verification Xilinx FPGA designs for Video Heads Up Displays. Test bench development using VHDL and Verilog.
Writing UVM Linting tool using Python to check UVM formatting, syntax, and usage of UVM Test Benches.
North Reading, Ma, Us
Developed system level UVM multi chip test bench for new Teradyne product that included two FPGA’s, and one ASSP with PCIE switch using Denali PCIE VIP including multi - casting.
Santa Clara, California, Us
Developed and specified OVM/UVM test benches, sequences, UVC’s, and tests for Intel’s server IP including PCIE Gen3. Supported customer developments and integration of Intel’s server based PCIE core into SOC/FPGA designs. Supported more than 10 sever/micro server designs. Key Accomplishments:• Initiated, planned, coded and managed PCIE3 OVM/UVM Test Bench Development• Developed OVM/UVM Sequences, Tests and Test Benches
Norcross, Georgia, Us
Telecom DWDM Systems Engineering Experience with G.709, SONET, Next Gen SONET, and EthernetDWDM Board Design Engineer Developed 3 high speed Circuit Packs
Fallbrook, Ca, Us
Defined and developed new innovative IP products for SOC based designs using reconfigurable Verilog, Perl and ARM Micro Processors which included configurable self checking test benches and Synthesis scripts.
San Jose, Ca, Us
Created an engineering group which provided expert ASIC design services for key tier one customers including RTL development, synthesis, static timing analysis, verification, floor planning, place and route, and scan insertion. Senior ASIC Library Development EngineerStreamlined and automated Standard Cell Library development process
Developed hardened Standard Cell Library and hardened Gate Arrays including program leader and planning.Key Accomplishments: • Lead Honeywell into #1 Radiation Hardened electrons positions over AT&T, LSI, TI, Harris and others• Patented Switching State Retention Circuit at Single Event Hardened Flip Flop Patent 3731119• Developed first configurable ASIC on chip memory
Other employees you can reach at intel.com. View company contacts for 10 employees →
Tali Polonsky Dayan
Colleague at Intel CorporationIsrael
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Stephen Walling
Colleague at Intel CorporationSan Diego, California, United States
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Conor Seery
Colleague at Intel CorporationIreland
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Li-Sheng Wang
Colleague at Intel CorporationBeaverton, Oregon, United States
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X旭
Xu 旭 Huang 黄
Colleague at Intel CorporationTokyo, Japan
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Janice Wallace
Colleague at Intel CorporationPortland, Oregon, United States
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Rebecca Robles
Colleague at Intel CorporationUnited States
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Monique M Rodriguez
Colleague at Intel CorporationCasa Grande, Arizona, United States
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Erez Milrad
Colleague at Intel CorporationNorth District, Israel
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Craig Bolton
Colleague at Intel CorporationChandler, Arizona, United States
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Quick answers generated from the profile data available on this page.
Billy Mills works for Intel Corporation.
Billy Mills is listed as Verification Engineer at Intel Corporation.
AeroLeads has found 1 work email signal at @intel.com for Billy Mills at Intel Corporation.
AeroLeads has found 2 phone signal(s) with area code 319 for Billy Mills at Intel Corporation.
Billy Mills is based in Hillsboro, Oregon, United States while working with Intel Corporation.
Billy Mills has worked for Intel Corporation, Rockwell Collins, Verif Pros, Teradyne, and Intel.
Billy Mills's colleagues at Intel Corporation include Tali Polonsky Dayan, Stephen Walling, Conor Seery, Li-Sheng Wang, and Xu 旭 Huang 黄.
You can use AeroLeads to view verified contact signals for Billy Mills at Intel Corporation, including work email, phone, and LinkedIn data when available.
Billy Mills holds Bsee, Electrical Engineering from The University Of New Mexico.
Billy Mills is listed with skills including Asic, Verilog, Systemverilog, Soc, Arm, Static Timing Analysis, Pcie, and Logic Synthesis.
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