Billy Repko Email & Phone Number

Chandler, Az

I am currently working in Advanced Power Systems doing design of digital Buck and Boost controllers for automotive products.

Chandler, Az

Work with mutil-media SOC's utilizing ATOM processors. Tasks include design and validation of low speed IO interfaces such as SPI, UART, GPIO, MMIO, and I2C. Worked on design and implementation of H264 Encoder bridge, SPI master, and MUTEX (Mutual Exclusivity) block. Tasks include microarchitecture, RTL implementation using Verilog, creation of test environment, creation and implementation of test plan, synthesis, gate level simulations, formal verification, and validation of the modules.

Chandler, Az

Worked on universal PHY design. Taks include Modeling analog circuit behavior, RTL implementation using Verilog, synthesis using Cadence tools, formal verification and validation.

Chandler, Az

Worked on SATA controller for Western Digital hard drives. Task include microarchitecture, design implementation using Verilog, synthesis, gate level simulations, formal verification, and validation. Worked on PCI Express universal PHY. Task include microarchitecture, design implementation using Verilog, and verification.

Chandler, Az

Worked on SRAM controller for IO storage devices. Worked on PCI Express logic for server chipsets. Tasks include microarchitecture, RTL implementation using Verilog, gate level simulation, synthesis, formal verification, and validation

Tempe, Az

Worked on DDR controller/arbitration logic for security coprocessor. Tasks include microarchitecture, RTL implementation, synthesis, formal verification, gate level simulations, creation of test environment, and validation.

Chander, Az

Worked as a product engineer on HP printer chips using Intel JX960 cores.Designed PCI slave module for Intel security products. Tasks include microarchitecture, RTL implementation, synthesis, validation, gate level simulations, and formal verification.Worked on PCIX master for Infiniband chip. Tasks include microarchitecture, RTL implementaion, validation, gate level simulations, formal verification, and synthesis.