Develop burn in modelling, evaluate burn in condition based on infant mortality DPM goal for FPGA products; Predict the burn in yield loss, qualification yield loss; Responsible for burn in yield loss analysis and product burn in health indicator; debug the root cause of low yield issue and disposition;Responsible for qualification failure analysis and burn in failiure analysis;Drive BI elimination for cost savings;

Take full ownership for CIS product qualification, from hardware design to reliability test implementation, until mass production release with full qualification; Debug the issues during reliability test, including FA, work with design/process/package/product team to find the root cause and take corrective action; Issue product qualification report and evaluation projects summaries; Deal with customer’s special reliability requirements and issue report;

Take full ownership of the product from tape out to NPR release, production ramp up and mass production; close work with TE, Design, PM, Marketing, Subcon, etc. to achieve NPR release with high quality and manufacturing robustness. including testing setup, Qual plan define and execution, skew/characterization analysis. Coordinate with internal team to optimize NPR flow and Qual strategy. Drive subcon & vendor to on-time deliver result. Maintain and optimize mass production, keep driving products’ yield improvement, deal with yield/process excursions, customers returned sample failure analysis; Continuous make efforts for cost down; Major Achievements： Drive 8 AP products NPR, including GF&SMIC 28nm products, coordinate with Designer/TE/QA/Planner to completed proto, Qualification, characterization, and release to production successfully. Support AP product (Jaguar) CP yield improve, drive Global Foundries to fine tune process window to balance the performance & power consumption tradeoff, improve yield from ~70% to 90%, and release the optimized process to all 28nm products;  Resolve lots of end product fail issue, like Lincoln DDR fail issue which resulted from Cu pillar bump location, ESD issue which resulted from weak IP design, OS issue which resulted from unreasonable CP probe card design, etc. Define NPR flow, create NPI control table to provide a schedule and milestone template, co-work with designer/TE/package/QA/Planner to optimize NPR release flow. Optimize company Qualification strategy: including Fab/Assy house Audit, ESD/Package Qual criteria, setup Qual database. Complete YMS system evaluation and trial, setup and release “Tango”. Cost reduction: like Lincoln&Maybach/JaguarB products, drive GPU low performance chip evaluation, work with end product/QA department, done product application development/reliability evaluation, finally released these samples to different application, rescued ~3% yield loss;

Take charge of 28nm technology BEOL process development; Cooperate with multi groups, including process/design rule/product/reliability/FA/mask shop, etc, define design rule, design test key, design process DOE, analyze WAT data, analyze fail sample, perform reliability test, drive 28nm BEOL process development smoothly; Tremendous hand on experiences on 28nm BEOL process and process integration; Oversee the process integration of OPC, litho, thin film, gap fill process, and gained an in-depth understanding of these areas;Major Achievement:• Led the efforts for 28nm Chip package interaction (CPI) evaluation, execution and qualification; Completed and passed 28nm Cu wire bonding BGA & Cu pillar flip chip package reliability;• Independently handled many new product tape outs; • Work with design rule team and complete BEOL design rule definition, compilation & verification; • Resolve lots of process defects, such as line bridge, line open, void, film delamination, particle; • Awarded “SMIC outstanding engineer” on 2013Q1；

Led the new material research, new product development, process improvement & some failure analysis; worked with multi group, including process/FA/reliability team, make sure mass production running smoothly, do failure analysis for fail parts, improve yield, analyze inline & WAT data, continuous make efforts for cost down; Major Achievements： Evaluated and impleted new substrate into mass production, cost down~10%;  Work with molding process engineer, resolved mold compound peeling issue, improved assembly yield ~2%;