Building and overseeing the Engineering team on multiple continents.Architecting and hands-on development of the next generation internet acceleration engine.Ensure on-time, quality delivery of products that result in high customer satisfaction.

Modeling and micro-architecture of the on-chip interconnection and hierarchical memory subsystem for the A-series SoC in iPhone and iPad.

CTO OfficeArchitected the PHY of a low power receiver for wireless sensor networks.

Architecture Group for Optical Storage System- Architected and led the development of a general purpose simulation platform. It could accommodate all the signal processing modules in the SoC, including the analog front-end, digital read channel and logical backend with ECC. This simulator is 100x faster than the original Simulink-based solution with only 1/100 of resource consumption. It is also bit and cycle accurate, easy to use. It played a crucial role for performance analysis and verification of the product.- Defined new signal processing and loop control algorithms to improve system performance. Ensure bug-free implementations in ASIC.- Led the architecture and design of the error-control coding and content protection subsystems.- Lab work on system bring-up. Supported the firmware development.

Taught:ECE 302 Probabilistic Methods in Electrical and Computer EngineeringECE 438 Digital Signal Processing with Applications

Worked on the wireless pen project.Wrote the Device Driver and middle-ware to enable the pen to work under Windows XP regular and Tablet PC editions.